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Rev Log message Author Age Path
64 BUG FIX: Flags CY and AC were not clear by logic instructions
Added new flag to microcode: clr_acy
Used new flag to clear AC and CY flags unconditonally
Modified microcode for XR*, OR* and AN* to use new flag
Modified microcode assembler to support new flag
Addex explaination of new flag to documentation
Old fix that worked only for XR* instructions removed
Test bench tb0 modified to test CY clearance minimally (AC untested!)
Pre-generated vhel test bench tb0 altered accordingly		 ja_rd 4465d 12h /
63 Modified syntax of ARGV parameter for compatibility to later versions of Perl ja_rd 4465d 12h /
62 Changed all hard tabs to spaces as preamble to a minor refactor ja_rd 4465d 21h /
61 Basic demo updated: main entity name changed to keep synthesis too happy ja_rd 4833d 23h /
60 Fixed nasty typo in pin constraints file (clock input) ja_rd 4838d 04h /
59 tabs to spaces ja_rd 4862d 11h /
58 tabs to spaces ja_rd 4862d 11h /
57 removed unfinished CPM demo files ja_rd 5047d 01h /
56 file list updated ja_rd 5047d 01h /
55 Altair 4K Basic demo on DE-1 board ja_rd 5047d 01h /
54 BUG FIX: XOR operations wre not clearing CY and ACY ja_rd 5047d 01h /
53 added interrupt for single-stepping
cleaned up comments a bit		 ja_rd 5403d 02h /
52 test bench compilation script sanitized a little ja_rd 5403d 02h /
51 interrupt test bench adapted to the fix in IE instruction ja_rd 5403d 02h /
50 interrupt test bench adapted to the fix in IE instruction ja_rd 5403d 02h /
49 fixed: IE now enables interrupts after a 1-instruction delay
(it was enabling interrupts immediately)		 ja_rd 5403d 02h /
48 clarification of some terms in the comments ja_rd 5403d 18h /
47 edited the file list and added a few remarks ja_rd 5403d 18h /
46 minor change in signal color for better readability ja_rd 5403d 18h /
45 Added modelsim scripts for the test benches ja_rd 5403d 18h /

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