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Rev	Log message	Author	Age	Path
90	Corrected small C compiler bug reported by Fred J. Scipione, Thanks!	motilito	3304d 13h	/
89	Specs document updated	ja_rd	4353d 11h	/
88	Changed interrupt controller to use RST instruction instead of CALL as interrupt vector. Some bug fixes to the c80 compiler.	motilito	4380d 15h	/
87	Added 8080EXER instruction exerciser demo for DE-1 board.	ja_rd	4393d 08h	/
86	Removed old C2SB files from previous location. Updated simulation script to use new directory for C2SB files.	ja_rd	4393d 08h	/
85	Moved all files common th the De-1 board demos to a new directory	ja_rd	4393d 08h	/
84	Added readme file to the 4kbasic code directory.	ja_rd	4393d 09h	/
83	4kbasic demo code deleted from old directory	ja_rd	4393d 09h	/
82	VHDL demo code reorganized: moved 4kbasic demo to new directory	ja_rd	4393d 09h	/
81	Removed backup file that shouldn't have been committed	ja_rd	4393d 09h	/
80	Improved usability of SoC (memory size calculation) Added comments to SoC code. Fixed starter kit board simulation test bench, added uart loopback	ja_rd	4393d 09h	/
79	DAA logic fixed and simplified	ja_rd	4393d 09h	/
78	Fixed a number of errors in the last refactor of the VHDL side of the project: - Path errors in the simulation scripts. - The reset pin in the C2SB mini-test-bench was not being driven. - The main vhdl test bench file was missing entirely. All of these errors due to not properly verifying the commit...	ja_rd	4399d 10h	/
77	Fixed a few mistakes in the last code reorganization. Mostly bad paths but also a broken comment in the UART source...	ja_rd	4400d 08h	/
76	Corrected some minor issues in the core description document.	motilito	4407d 00h	/
75	Updated file list	ja_rd	4410d 15h	/
74	Testbenches for VHDL core moved to sw/tb. Added a mini-demo for the VHDL SoC on the DE-1 dev board. Added a mini-testbench for the VHDL SoC.	ja_rd	4410d 16h	/
73	New tool for VHDL object code constant generation. Old VHDL template tool moved to tools directory.	ja_rd	4410d 16h	/
72	Added specs document for VHDL/Verilog CPU core	ja_rd	4410d 16h	/
71	IMSAI manual removed, no longer used	ja_rd	4410d 16h	/
70	Added new VHDL SoC for demonstration purposes	ja_rd	4410d 16h	/
69	New simulation scripts for Modelsim in new separate directory. Includes old test benches for CPU VHDL core and new test benches for SoC VHDL core	ja_rd	4410d 16h	/
68	Corrected ihex2vlog tool to enable explicit RAM declaration for Spartan 2.	motilito	4421d 11h	/
67	Corrected bugs in the Small-C compiler.	motilito	4422d 14h	/
66	Adding interrupt example code to the Verilog implementation. An interrupt controller was added to the sample SOC module and a sample code was added to the "hello.c" example code.	motilito	4437d 11h	/
65	Adding Verilog initial version to the svn. Added the c80 Small-C compiler and AS80 assembler.	motilito	4448d 19h	/
64	BUG FIX: Flags CY and AC were not clear by logic instructions Added new flag to microcode: clr_acy Used new flag to clear AC and CY flags unconditonally Modified microcode for XR, OR and AN* to use new flag Modified microcode assembler to support new flag Addex explaination of new flag to documentation Old fix that worked only for XR* instructions removed Test bench tb0 modified to test CY clearance minimally (AC untested!) Pre-generated vhel test bench tb0 altered accordingly	ja_rd	4457d 19h	/
63	Modified syntax of ARGV parameter for compatibility to later versions of Perl	ja_rd	4457d 19h	/
62	Changed all hard tabs to spaces as preamble to a minor refactor	ja_rd	4458d 05h	/
61	Basic demo updated: main entity name changed to keep synthesis too happy	ja_rd	4826d 06h	/

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