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Rev	Log message	Author	Age	Path
28	updated doc	mikel262	5528d 09h	/
27	Inserted multiple stage pipeline for final adders to improve greatly performance with expense of area.	mikel262	5528d 10h	/
26	Added old uploaded documents to new repository.	root	5535d 15h	/
25	Added old uploaded documents to new repository.	root	5536d 04h	/
24	New directory structure.	root	5536d 04h	/
23	This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_8'.		5538d 10h	/
22	project released under LGPL	mikel262	5538d 10h	/
21	Fix for XST synthesis error and improve readibility (by Andreas Bergmann).	mikel262	5538d 11h	/
20	Fix for XST synthesis error and improve readibility (by Andreas Bergman).	mikel262	5538d 11h	/
19	This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_6'.		6563d 07h	/
18	Minor fixes. This release is FPGA proven.	mikel262	6563d 07h	/
17	This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_5'.		6585d 03h	/
16	Documentation update, minor fixes	mikel262	6585d 03h	/
15	Redesigned. Fully pipelined, always ready for data design	mikel262	6585d 05h	/
14	This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_4'.		6589d 04h	/
13	performance improved by 8%, latency reduced to 94 cycles	mikel262	6589d 04h	/
12	This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_3'.		6590d 03h	/
11	changed ROM memory model to synchronous	mikel262	6590d 03h	/
10	+ moved memory allocation request to where it should be + reduced latency to 104 cycles	mikel262	6591d 05h	/
9	This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_2'.		6593d 16h	/

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