URL https://opencores.org/ocsvn/mem_ctrl/mem_ctrl/trunk

Subversion Repositories mem_ctrl

[/] [mem_ctrl/] [trunk/] - Rev 28

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Rev	Log message	Author	Age	Path
28	New directory structure.	root	5526d 20h	/mem_ctrl/trunk/
27	Initial release	rherveille	8087d 05h	/trunk/
26	Initial release	rherveille	8087d 05h	/trunk/
25	Initial release	rherveille	8087d 06h	/trunk/
24	* empty log message *	rudi	8131d 07h	/trunk/
23	* empty log message *	rudi	8131d 08h	/trunk/
22	Fixed several minor bugs, cleaned up the code further ...	rudi	8131d 08h	/trunk/
21	Updated Spec ...	rudi	8137d 20h	/trunk/
20	- Fixed combinatorial loops in synthesis - Fixed byte select bug	rudi	8162d 16h	/trunk/
19	* empty log message *	rudi	8171d 14h	/trunk/
18	- Made some changes not to expect clock during reset ...	rudi	8172d 18h	/trunk/
17	- Updated Documentation - More Synthesis cleanup, mostly for speed - Several bug fixes - Changed code to avoid auto-precharge and burst-terminate combinations (apparently illegal ?) Now we will do a manual precharge ...	rudi	8184d 18h	/trunk/
16	- More Synthesis cleanup, mostly for speed - Several bug fixes - Changed code to avoid auto-precharge and burst-terminate combinations (apparently illegal ?) Now we will do a manual precharge ...	rudi	8184d 18h	/trunk/
15	Just minor test bench update, syncing all the files.	rudi	8200d 20h	/trunk/
14	Minor fixes to testbench ...	rudi	8202d 19h	/trunk/
13	Fixed Register reads Tightened up timing for register rd/wr	rudi	8240d 17h	/trunk/
12	Changed Reset to be active high and async.	rudi	8250d 20h	/trunk/
11	* empty log message *	rudi	8264d 07h	/trunk/
10	Fixed the TMS register setup to be tight and correct.	rudi	8272d 18h	/trunk/
9	Many fixes for minor bugs that showed up in gate level simulations.	rudi	8272d 18h	/trunk/

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Subversion Repositories mem_ctrl

[/] [mem_ctrl/] [trunk/] - Rev 28

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