URL https://opencores.org/ocsvn/minimips_superscalar/minimips_superscalar/trunk

Subversion Repositories minimips_superscalar

[/] - Rev 36

Rev	Log message	Author	Age	Path
36	update pc	mcafruni	1510d 07h	/
35	New delay_gate.vhd	mcafruni	1513d 02h	/
34	Delete delay_gate to upload a new one.	mcafruni	1513d 02h	/
33	New syscop.vhd	mcafruni	1513d 02h	/
32	Delete syscop to upload a new one.	mcafruni	1513d 02h	/
31	New top module.	mcafruni	1513d 02h	/
30	Delete top module to upload a new one.	mcafruni	1513d 02h	/
29	New banc register file.	mcafruni	1513d 02h	/
28	Delete banc.vhd to upload a new one.	mcafruni	1513d 02h	/
27	New bench on P1 tag.	mcafruni	1513d 02h	/
26	Delete bench to upload a new one.	mcafruni	1513d 02h	/
25	New bench	mcafruni	1513d 02h	/
24	Delete bench to upload a new one.	mcafruni	1513d 02h	/
23	Moving the benchmarks folder into the trunk folder.	mcafruni	1518d 21h	/
22	Wrong code. (fi0.bin) But revealed a bug that needs attention.	mcafruni	1518d 21h	/
21	Correcting codes that work in behavioral simulation but cause problems with implementation. There must be more to be corrected yet. In analysis ...	mcafruni	1518d 21h	/
20	I've uncommented wait statement so that the benchmark to be loaded into the simulation.	mcafruni	1553d 09h	/
19		mcafruni	1887d 01h	/
18	clock_gate.vhd: removed. minimips.vhd: Clock2 input is wrongly connected to the clock signal (Do not ask me how that happened. I'm sorry.). The right thing is to be connected to the clock2 signal. Adjusted.	mcafruni	1887d 01h	/
17	Removing unnecessary clock-gate architecture.	mcafruni	1887d 02h	/