URL https://opencores.org/ocsvn/minimips_superscalar/minimips_superscalar/trunk

Subversion Repositories minimips_superscalar

[/] - Rev 6

Rev	Log message	Author	Age	Path
6	This is the assembly gasm modified that include a multiplication instruction which operands are 16-bit wide.	mcafruni	1956d 15h	/
5	6x6 Matrix multiplication (ingenuous algorithm) msx.bin: uses 16-bit operands multiplication instruction (mult2 rd, rs, rt). m6x.bin: uses 32-bit operands original multiplication instruction (mult rs, rt) and the move instruction (mflo rd) after.	mcafruni	1956d 23h	/
4	It needs to be tested on more useful and real benchmarks to reveal possible instruction sequences not supported by the architecture. Suggestions are welcome.	mcafruni	1956d 23h	/
3		mcafruni	1956d 23h	/
2		mcafruni	1957d 00h	/
1	The project and the structure was created	root	1957d 10h	/