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Rev Log message Author Age Path
92 backend/spartan3e_starter_kit*: or1200_defines.v file was outdated and hindering synthesis. Probably it would be best if we used a patching system here. But for now, I copied the new files and made the necessary changes to fit the system into the target boards. rfajardo 4611d 12h /
91 prj/scripts/: Changing scripts not to include multiple timescale.v files from different listed directories in the project definition file. Instead, now the internal loop which look for the file in different directories is broken when the first file is found. rfajardo 4611d 13h /
90 After minsoc_top.prj update, make regenerated src and xst files. rfajardo 4612d 05h /
89 minsoc_top.prj was splited into minsoc_top and minsoc_bench. minsoc_top still had directory entries of bench, they are gone now. rfajardo 4612d 05h /
88 Project structure, Xilinx Makefiles and simulation working. rfajardo 4612d 05h /
87 Synchronizing scripts to behave exactly the same. rfajardo 4612d 06h /
86 Updating configure script messages. rfajardo 4612d 06h /
85 Central project definition under prj. Synthesis and simulation take their project files from here. rfajardo 4612d 06h /
84 syn/blackboxes/eth_top.v:
-module is now called ethmac instead of eth_top
-eth_defines.v is now called ethmac_defines.v
rfajardo 4613d 07h /
83 minsoc-install.sh: bzip2 program was being used, but its existance on target system was not being verified. It is now. rfajardo 4624d 12h /

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