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Subversion Repositories minsoc

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Rev Log message Author Age Path
119 Tricking Subversion to accept bat files that are now executable. rfajardo 3285d 13h /
118 Configure scripts for Xilinx devices updated. All of them require to update or1200_defines.v. The non-standard part uses now the variable $BOARD to print that this board require non-standard update of files. rfajardo 3285d 13h /
117 spartan3e_starter_kit designs require DUALPORT from or1200_defines.v to be active instead of GENERIC. rfajardo 3285d 14h /
116 Configure scripts were trying to copy/patch projects files before creating them. Ordering is correct now. rfajardo 3285d 14h /
115 configure.sh script dir aware.
minsoc-install.sh logging to script dir.
rfajardo 3285d 15h /
114 Installation and Configuration scripts can be run out of any directory.
They assume they are going to process the files and directories found in the directory they are run from.
rfajardo 3285d 15h /
113 minsoc-install.sh & minsoc-configure.sh:
-aware of location of configure.sh script
configure.sh:
-does not block on patch error

spartan3e_starter_kit & spartan3e_starter_kit_eth:
-or1200_defines.v updated

prj:
-src/blackboxes/or1200_top.v adjusted to or1200_rel1
-Makefile had a typo regarding altera vhdl files
rfajardo 3285d 15h /
112 Updating installation & configuration scripts. rfajardo 3286d 06h /
111 minsoc-install.sh: DIR_TO_INSTALL is required before using beautify.sh rfajardo 3286d 07h /
110 Fixing several minor issues with the system:
-minsoc-install splitted into installation and configuration
-minsoc-configure.sh can be used to configure a fresh checked out system
-configure script used by both minsoc-configure.sh and minsoc-install.sh to configure

-rtl/verilog: svn externals fixed
-or1200 rolled back to release-1.0

-prj/scripts:
-Makefile has been used by simulation to differentiate project definition of vhdl and verilog files
-Altera was differentiating it in script
-now there are two scripts, one for vhdl and another for verilog. The differentiation occurs in Makefile as for simulation.
-altera_3c25_board/configure scripts had to be updated, vprj and vhdprj file extensions used to differentiate Verilog and VHDL project files.

-prj/src: or1200_top.prj downdated to definition of or1200_v1
rfajardo 3286d 07h /

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