| Rev |
Log message |
Author |
Age |
Path |
| 167 |
Ruben Diez fix to installation script problem in Windows:
minsoc-install.sh breaks if there are spaces in the PATH, which is rather common under Cygwin, as most Windows PCs have something like "C:\Program Files" in there. |
rfajardo |
4372d 09h |
/ |
| 166 |
Turning on warnings for genera_bench.
Updating minsoc-install.sh to work better with directories and working around a missing inclusion of libftdi autotools. http://opencores.org/forum,OpenRISC,0,4685,1 |
rfajardo |
4386d 08h |
/ |
| 165 |
Board contribution: nexys2_1200 (Thanks to Johan Granath)
spartan3e_starter_kit_eth/minsoc_bench_defines.v: deprecated definition updated |
rfajardo |
4403d 09h |
/ |
| 164 |
Updating width of minsoc_tc_top.v for Wishbone B3 compliance. This file has never worked. This solves at least the bug that some signals were not being routed through. |
rfajardo |
4468d 01h |
/ |
| 163 |
Adjusting internal initiator array widths. They were 1 bit too large. Thanks to R. Diez report.
These arrays abstract the complete initiator inputs. This way it is easier to route and arbiter using a single input.
Also removing 2 sequential delays. I didn't design them, so I can't tell if they were really useful/good. |
rfajardo |
4474d 08h |
/ |
| 162 |
Tasks don't have parenthesis. This is only used for ports on modules. This was a mistake from my part. |
rfajardo |
4480d 03h |
/ |
| 161 |
Correcting configure parameters of adv_jtag_bridge on installation script. |
rfajardo |
4493d 06h |
/ |
| 160 |
Typo in minsoc-install.sh script. Adv_jtag_bridge was not configuring correctly. |
rfajardo |
4493d 06h |
/ |
| 159 |
Updated constraint file for de2_115 board. (Richard Hasha) |
rfajardo |
4493d 07h |
/ |
| 158 |
Adding de2_115_board port, thanks to Richard Hasha.
Support to JSP (JTAG Serial Port) working well. Also provided by Richard Hasha.
Different interconnect configurations per board are not straightforward on MinSoC. New added modules or definitions for addresses have to be carried over to other boards. Furthermore, extra modules can be shared among all projects. Thus, it is better to have this centralized:
-Removing interconnect configuration from minsoc_defines.v. There is an interconnect_defines.v file on rtl/verilog. The software counterpart is interconnect.h on sw/drivers.
Including a jsp firmware. It is basically the uart firmware but using JSP instead. Added to all board configure scripts to be compiled on configuration.
prj/srcs extended to include jsp and interconnec_defines.v.
spartan3e_starter_kit_eth lost UART (does not fit) and uses JSP instead now. |
rfajardo |
4494d 23h |
/ |
| 157 |
Removed obsolete file; the changes in this version have been merged into
the mainline advanced debug system version 3.0 and higher. |
nyawn |
4500d 18h |
/ |
| 156 |
Added hardware watchpoint indicators to debug unit break input, to allow
the debugger to break when a hardware watchpoint is triggered. |
nyawn |
4500d 18h |
/ |
| 155 |
Decreased wait time, for faster simulations. |
nyawn |
4500d 18h |
/ |
| 154 |
Modified to use the new autotools support in the advanced debug system v3.0. |
nyawn |
4500d 18h |
/ |
| 153 |
Updating installation script to download minsoc from this branche, verilator, instead of rc-1.0. |
rfajardo |
4533d 07h |
/ |
| 152 |
Roll back to retrieve minsoc from branches/rc-1.0. |
rfajardo |
4533d 08h |
/ |
| 151 |
Creating tag release-1.0 from revision 150 of branches/rc-1.0. |
rfajardo |
4533d 08h |
/ |
| 150 |
Updating installation script to retrieve minsoc from tags/release-1.0. |
rfajardo |
4533d 08h |
/ |
| 149 |
Merging differences of release candidate 1.0 revision 140:148 with trunk. |
rfajardo |
4533d 08h |
/ |
| 148 |
Renaming minsoc_wave.lxt to minsoc_wave.lxt2 for correctness. |
rfajardo |
4538d 04h |
/ |
