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Rev Log message Author Age Path
102 GNU GDB FTP has renamed gdb-6.8 package to gdb-6.8a package. Uncompressed it remains gdb-6.8, so no other changes to script are necessary. rfajardo 3021d 02h /minsoc/
101 Documentation, wiki's address updated. rfajardo 3046d 14h /minsoc/
100 syn/altera/minsoc_top.qsf: I thought this file was being generated now as project file description. But it is merely a synthesis configuration file and must be here. File re-added. rfajardo 3055d 11h /minsoc/
99 backend/altera_3c25_board/minsoc_defines.v: if GENERIC_FPGA selected, undefine ALTERA_FPGA and FPGA_FAMILY to avoid vendor specific code to flow into the simulation. If you don't do it, generate_bench fails. rfajardo 3055d 11h /minsoc/
98 Removing deprecated minsoc_top.qsf file. rfajardo 3055d 12h /minsoc/
97 As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. rfajardo 3055d 12h /minsoc/
96 Some files needed for Altera synthesis javieralso 3055d 23h /minsoc/
95 Makefile for Altera FPGAs fixed javieralso 3057d 02h /minsoc/
94 Fix bug in minsoc_top.prj for Altera synthesis javieralso 3059d 11h /minsoc/
93 Support for Altera synthesis. It needs some tune, but it works fine javieralso 3059d 13h /minsoc/
92 backend/spartan3e_starter_kit*: or1200_defines.v file was outdated and hindering synthesis. Probably it would be best if we used a patching system here. But for now, I copied the new files and made the necessary changes to fit the system into the target boards. rfajardo 3060d 11h /minsoc/
91 prj/scripts/: Changing scripts not to include multiple timescale.v files from different listed directories in the project definition file. Instead, now the internal loop which look for the file in different directories is broken when the first file is found. rfajardo 3060d 12h /minsoc/
90 After minsoc_top.prj update, make regenerated src and xst files. rfajardo 3061d 04h /minsoc/
89 minsoc_top.prj was splited into minsoc_top and minsoc_bench. minsoc_top still had directory entries of bench, they are gone now. rfajardo 3061d 04h /minsoc/
88 Project structure, Xilinx Makefiles and simulation working. rfajardo 3061d 04h /minsoc/
87 Synchronizing scripts to behave exactly the same. rfajardo 3061d 05h /minsoc/
86 Updating configure script messages. rfajardo 3061d 05h /minsoc/
85 Central project definition under prj. Synthesis and simulation take their project files from here. rfajardo 3061d 05h /minsoc/
84 syn/blackboxes/eth_top.v:
-module is now called ethmac instead of eth_top
-eth_defines.v is now called ethmac_defines.v
rfajardo 3062d 06h /minsoc/
83 minsoc-install.sh: bzip2 program was being used, but its existance on target system was not being verified. It is now. rfajardo 3073d 11h /minsoc/

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