| Rev |
Log message |
Author |
Age |
Path |
| 106 |
Installation script was checking the ENV variable before setting it. |
rfajardo |
4358d 19h |
/minsoc/ |
| 105 |
Updating configure scripts to copy Windows synthesis launch script setup.bat from either minsoc/syn/altera or minsoc/syn/xilinx to minsoc/syn. |
rfajardo |
4358d 20h |
/minsoc/ |
| 104 |
Enabling modelsim simulation for current project definition.
vhdl and verilog projects have to be separated:
-prj/Makefile defines VHDL_PROJECTS and VERILOG_PROJECTS, they are merged into PROJECTS. Tools which don't care about VHDL or Verilog use PROJECTS list while other tools use VERILOG_ or VHDL_PROJECTS.
-Simulation uses VHDL_PROJECTS and VERILOG_PROJECTS independently.
-prj/scripts/simprj.sh splitted in:
-simvhdl.sh
-simverilog.sh
(they generate the input files in the right format for simulation tools) |
rfajardo |
4365d 19h |
/minsoc/ |
| 103 |
But the file is called gdb-6.8a.tar.bz2, so tar must be run on that name. |
rfajardo |
4368d 10h |
/minsoc/ |
| 102 |
GNU GDB FTP has renamed gdb-6.8 package to gdb-6.8a package. Uncompressed it remains gdb-6.8, so no other changes to script are necessary. |
rfajardo |
4368d 10h |
/minsoc/ |
| 101 |
Documentation, wiki's address updated. |
rfajardo |
4393d 22h |
/minsoc/ |
| 100 |
syn/altera/minsoc_top.qsf: I thought this file was being generated now as project file description. But it is merely a synthesis configuration file and must be here. File re-added. |
rfajardo |
4402d 20h |
/minsoc/ |
| 99 |
backend/altera_3c25_board/minsoc_defines.v: if GENERIC_FPGA selected, undefine ALTERA_FPGA and FPGA_FAMILY to avoid vendor specific code to flow into the simulation. If you don't do it, generate_bench fails. |
rfajardo |
4402d 20h |
/minsoc/ |
| 98 |
Removing deprecated minsoc_top.qsf file. |
rfajardo |
4402d 20h |
/minsoc/ |
| 97 |
As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. |
rfajardo |
4402d 21h |
/minsoc/ |
| 96 |
Some files needed for Altera synthesis |
javieralso |
4403d 07h |
/minsoc/ |
| 95 |
Makefile for Altera FPGAs fixed |
javieralso |
4404d 10h |
/minsoc/ |
| 94 |
Fix bug in minsoc_top.prj for Altera synthesis |
javieralso |
4406d 19h |
/minsoc/ |
| 93 |
Support for Altera synthesis. It needs some tune, but it works fine |
javieralso |
4406d 22h |
/minsoc/ |
| 92 |
backend/spartan3e_starter_kit*: or1200_defines.v file was outdated and hindering synthesis. Probably it would be best if we used a patching system here. But for now, I copied the new files and made the necessary changes to fit the system into the target boards. |
rfajardo |
4407d 20h |
/minsoc/ |
| 91 |
prj/scripts/: Changing scripts not to include multiple timescale.v files from different listed directories in the project definition file. Instead, now the internal loop which look for the file in different directories is broken when the first file is found. |
rfajardo |
4407d 21h |
/minsoc/ |
| 90 |
After minsoc_top.prj update, make regenerated src and xst files. |
rfajardo |
4408d 12h |
/minsoc/ |
| 89 |
minsoc_top.prj was splited into minsoc_top and minsoc_bench. minsoc_top still had directory entries of bench, they are gone now. |
rfajardo |
4408d 12h |
/minsoc/ |
| 88 |
Project structure, Xilinx Makefiles and simulation working. |
rfajardo |
4408d 13h |
/minsoc/ |
| 87 |
Synchronizing scripts to behave exactly the same. |
rfajardo |
4408d 14h |
/minsoc/ |
