| Rev |
Log message |
Author |
Age |
Path |
| 123 |
Renaming reg final to firmware_size. Final is a keyword for Verilator. |
rfajardo |
4343d 23h |
/minsoc/ |
| 122 |
Renaming minsoc-configure.sh to minsoc-setup.sh. |
rfajardo |
4349d 12h |
/minsoc/ |
| 121 |
Asserting svn:executable properties of modelsim/*.bat scripts.
Including corrected patch for advanced debug system watchpoints under utils/setup. Configure script updated to use this instead of advanced debug system patches. This will remain so until the patch is corrected. The previous line still has the correct command. |
rfajardo |
4349d 14h |
/minsoc/ |
| 120 |
ethmac.prj: a file was missing |
rfajardo |
4349d 16h |
/minsoc/ |
| 119 |
Tricking Subversion to accept bat files that are now executable. |
rfajardo |
4349d 17h |
/minsoc/ |
| 118 |
Configure scripts for Xilinx devices updated. All of them require to update or1200_defines.v. The non-standard part uses now the variable $BOARD to print that this board require non-standard update of files. |
rfajardo |
4349d 17h |
/minsoc/ |
| 117 |
spartan3e_starter_kit designs require DUALPORT from or1200_defines.v to be active instead of GENERIC. |
rfajardo |
4349d 18h |
/minsoc/ |
| 116 |
Configure scripts were trying to copy/patch projects files before creating them. Ordering is correct now. |
rfajardo |
4349d 18h |
/minsoc/ |
| 115 |
configure.sh script dir aware.
minsoc-install.sh logging to script dir. |
rfajardo |
4349d 19h |
/minsoc/ |
| 114 |
Installation and Configuration scripts can be run out of any directory.
They assume they are going to process the files and directories found in the directory they are run from. |
rfajardo |
4349d 19h |
/minsoc/ |
| 113 |
minsoc-install.sh & minsoc-configure.sh:
-aware of location of configure.sh script
configure.sh:
-does not block on patch error
spartan3e_starter_kit & spartan3e_starter_kit_eth:
-or1200_defines.v updated
prj:
-src/blackboxes/or1200_top.v adjusted to or1200_rel1
-Makefile had a typo regarding altera vhdl files |
rfajardo |
4349d 19h |
/minsoc/ |
| 112 |
Updating installation & configuration scripts. |
rfajardo |
4350d 11h |
/minsoc/ |
| 111 |
minsoc-install.sh: DIR_TO_INSTALL is required before using beautify.sh |
rfajardo |
4350d 11h |
/minsoc/ |
| 110 |
Fixing several minor issues with the system:
-minsoc-install splitted into installation and configuration
-minsoc-configure.sh can be used to configure a fresh checked out system
-configure script used by both minsoc-configure.sh and minsoc-install.sh to configure
-rtl/verilog: svn externals fixed
-or1200 rolled back to release-1.0
-prj/scripts:
-Makefile has been used by simulation to differentiate project definition of vhdl and verilog files
-Altera was differentiating it in script
-now there are two scripts, one for vhdl and another for verilog. The differentiation occurs in Makefile as for simulation.
-altera_3c25_board/configure scripts had to be updated, vprj and vhdprj file extensions used to differentiate Verilog and VHDL project files.
-prj/src: or1200_top.prj downdated to definition of or1200_v1 |
rfajardo |
4350d 12h |
/minsoc/ |
| 109 |
Creating a branche for release candidate 1.0. |
rfajardo |
4350d 13h |
/minsoc/ |
| 108 |
Scripts updates to correct paths when working under Windows. Now, ModelSim, Xilinx and Altera synthesis are working on Windows through batch files.
Icarus Verilog and Altera synthesis are working as well. Job done! |
rfajardo |
4350d 16h |
/minsoc/ |
| 107 |
Adding setup batch script for Altera synthesis on Windows.
prj/scripts/altprj.sh has now to check if it is run from cygwin in order to re-formulate the path to windows system.
Maybe the other scripts have to be updated too. This will be checked soon. |
rfajardo |
4350d 19h |
/minsoc/ |
| 106 |
Installation script was checking the ENV variable before setting it. |
rfajardo |
4350d 22h |
/minsoc/ |
| 105 |
Updating configure scripts to copy Windows synthesis launch script setup.bat from either minsoc/syn/altera or minsoc/syn/xilinx to minsoc/syn. |
rfajardo |
4351d 00h |
/minsoc/ |
| 104 |
Enabling modelsim simulation for current project definition.
vhdl and verilog projects have to be separated:
-prj/Makefile defines VHDL_PROJECTS and VERILOG_PROJECTS, they are merged into PROJECTS. Tools which don't care about VHDL or Verilog use PROJECTS list while other tools use VERILOG_ or VHDL_PROJECTS.
-Simulation uses VHDL_PROJECTS and VERILOG_PROJECTS independently.
-prj/scripts/simprj.sh splitted in:
-simvhdl.sh
-simverilog.sh
(they generate the input files in the right format for simulation tools) |
rfajardo |
4357d 23h |
/minsoc/ |
| 103 |
But the file is called gdb-6.8a.tar.bz2, so tar must be run on that name. |
rfajardo |
4360d 14h |
/minsoc/ |
| 102 |
GNU GDB FTP has renamed gdb-6.8 package to gdb-6.8a package. Uncompressed it remains gdb-6.8, so no other changes to script are necessary. |
rfajardo |
4360d 14h |
/minsoc/ |
| 101 |
Documentation, wiki's address updated. |
rfajardo |
4386d 02h |
/minsoc/ |
| 100 |
syn/altera/minsoc_top.qsf: I thought this file was being generated now as project file description. But it is merely a synthesis configuration file and must be here. File re-added. |
rfajardo |
4395d 00h |
/minsoc/ |
| 99 |
backend/altera_3c25_board/minsoc_defines.v: if GENERIC_FPGA selected, undefine ALTERA_FPGA and FPGA_FAMILY to avoid vendor specific code to flow into the simulation. If you don't do it, generate_bench fails. |
rfajardo |
4395d 00h |
/minsoc/ |
| 98 |
Removing deprecated minsoc_top.qsf file. |
rfajardo |
4395d 00h |
/minsoc/ |
| 97 |
As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. |
rfajardo |
4395d 00h |
/minsoc/ |
| 96 |
Some files needed for Altera synthesis |
javieralso |
4395d 11h |
/minsoc/ |
| 95 |
Makefile for Altera FPGAs fixed |
javieralso |
4396d 14h |
/minsoc/ |
| 94 |
Fix bug in minsoc_top.prj for Altera synthesis |
javieralso |
4398d 23h |
/minsoc/ |
