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[/] [minsoc/] - Rev 129

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Rev Log message Author Age Path
129 Removing bugs introduced when splitting clocks and reset.
1) NEGATIVE_RESET or POSITIVE_RESET were missing as definition on minsoc_bench_clock.v (include minsoc_defines.v).
2) wait for reset on minsoc_bench.v to assert design_ready
rfajardo 3281d 12h /minsoc/
128 Outsourcing clocks and reset generations from minsoc_bench.v to minsoc_bench_clock.v. rfajardo 3281d 12h /minsoc/
127 Removing redundant simulation output. rfajardo 3281d 19h /minsoc/
126 Updating information about simulation time for Ethernet test. rfajardo 3281d 19h /minsoc/
125 Adjusting testbench messages. Creating tasks for firmware tests. rfajardo 3281d 19h /minsoc/
124 Removing Verilog delays from minsoc_bench.v. minsoc_bench_defines.v defines now if uart or ethernet have to be tested. If yes, it checks the behavior of the enclosed firmwares. If not, simulation simply runs forever. rfajardo 3281d 21h /minsoc/
123 Renaming reg final to firmware_size. Final is a keyword for Verilator. rfajardo 3282d 02h /minsoc/
122 Renaming minsoc-configure.sh to minsoc-setup.sh. rfajardo 3287d 15h /minsoc/
121 Asserting svn:executable properties of modelsim/*.bat scripts.

Including corrected patch for advanced debug system watchpoints under utils/setup. Configure script updated to use this instead of advanced debug system patches. This will remain so until the patch is corrected. The previous line still has the correct command.
rfajardo 3287d 17h /minsoc/
120 ethmac.prj: a file was missing rfajardo 3287d 19h /minsoc/
119 Tricking Subversion to accept bat files that are now executable. rfajardo 3287d 20h /minsoc/
118 Configure scripts for Xilinx devices updated. All of them require to update or1200_defines.v. The non-standard part uses now the variable $BOARD to print that this board require non-standard update of files. rfajardo 3287d 20h /minsoc/
117 spartan3e_starter_kit designs require DUALPORT from or1200_defines.v to be active instead of GENERIC. rfajardo 3287d 21h /minsoc/
116 Configure scripts were trying to copy/patch projects files before creating them. Ordering is correct now. rfajardo 3287d 21h /minsoc/
115 configure.sh script dir aware.
minsoc-install.sh logging to script dir.
rfajardo 3287d 22h /minsoc/
114 Installation and Configuration scripts can be run out of any directory.
They assume they are going to process the files and directories found in the directory they are run from.
rfajardo 3287d 22h /minsoc/
113 minsoc-install.sh & minsoc-configure.sh:
-aware of location of configure.sh script
configure.sh:
-does not block on patch error

spartan3e_starter_kit & spartan3e_starter_kit_eth:
-or1200_defines.v updated

prj:
-src/blackboxes/or1200_top.v adjusted to or1200_rel1
-Makefile had a typo regarding altera vhdl files
rfajardo 3287d 22h /minsoc/
112 Updating installation & configuration scripts. rfajardo 3288d 13h /minsoc/
111 minsoc-install.sh: DIR_TO_INSTALL is required before using beautify.sh rfajardo 3288d 14h /minsoc/
110 Fixing several minor issues with the system:
-minsoc-install splitted into installation and configuration
-minsoc-configure.sh can be used to configure a fresh checked out system
-configure script used by both minsoc-configure.sh and minsoc-install.sh to configure

-rtl/verilog: svn externals fixed
-or1200 rolled back to release-1.0

-prj/scripts:
-Makefile has been used by simulation to differentiate project definition of vhdl and verilog files
-Altera was differentiating it in script
-now there are two scripts, one for vhdl and another for verilog. The differentiation occurs in Makefile as for simulation.
-altera_3c25_board/configure scripts had to be updated, vprj and vhdprj file extensions used to differentiate Verilog and VHDL project files.

-prj/src: or1200_top.prj downdated to definition of or1200_v1
rfajardo 3288d 14h /minsoc/

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