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[/] [minsoc/] - Rev 150

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130 minsoc_bench.v: task test_eth has to be phased out together with the ETHERNET definition. If there is no ETHERNET, test_eth cannot be defined. rfajardo 4566d 08h /minsoc
129 Removing bugs introduced when splitting clocks and reset.
1) NEGATIVE_RESET or POSITIVE_RESET were missing as definition on minsoc_bench_clock.v (include minsoc_defines.v).
2) wait for reset on minsoc_bench.v to assert design_ready		 rfajardo 4566d 19h /minsoc
128 Outsourcing clocks and reset generations from minsoc_bench.v to minsoc_bench_clock.v. rfajardo 4566d 20h /minsoc
127 Removing redundant simulation output. rfajardo 4567d 02h /minsoc
126 Updating information about simulation time for Ethernet test. rfajardo 4567d 02h /minsoc
125 Adjusting testbench messages. Creating tasks for firmware tests. rfajardo 4567d 02h /minsoc
124 Removing Verilog delays from minsoc_bench.v. minsoc_bench_defines.v defines now if uart or ethernet have to be tested. If yes, it checks the behavior of the enclosed firmwares. If not, simulation simply runs forever. rfajardo 4567d 04h /minsoc
123 Renaming reg final to firmware_size. Final is a keyword for Verilator. rfajardo 4567d 09h /minsoc
122 Renaming minsoc-configure.sh to minsoc-setup.sh. rfajardo 4572d 22h /minsoc
121 Asserting svn:executable properties of modelsim/*.bat scripts.

Including corrected patch for advanced debug system watchpoints under utils/setup. Configure script updated to use this instead of advanced debug system patches. This will remain so until the patch is corrected. The previous line still has the correct command.		 rfajardo 4573d 00h /minsoc

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