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132 ModelSim simulation, running top_module minsoc_bench_clock now, instead of minsoc_bench. rfajardo 4592d 07h /minsoc/
131 Renaming testbench modules. Adding to ifdefs without which the testbench generation can fail. rfajardo 4592d 07h /minsoc/
130 minsoc_bench.v: task test_eth has to be phased out together with the ETHERNET definition. If there is no ETHERNET, test_eth cannot be defined. rfajardo 4592d 09h /minsoc/
129 Removing bugs introduced when splitting clocks and reset.
1) NEGATIVE_RESET or POSITIVE_RESET were missing as definition on minsoc_bench_clock.v (include minsoc_defines.v).
2) wait for reset on minsoc_bench.v to assert design_ready
rfajardo 4592d 21h /minsoc/
128 Outsourcing clocks and reset generations from minsoc_bench.v to minsoc_bench_clock.v. rfajardo 4592d 21h /minsoc/
127 Removing redundant simulation output. rfajardo 4593d 03h /minsoc/
126 Updating information about simulation time for Ethernet test. rfajardo 4593d 04h /minsoc/
125 Adjusting testbench messages. Creating tasks for firmware tests. rfajardo 4593d 04h /minsoc/
124 Removing Verilog delays from minsoc_bench.v. minsoc_bench_defines.v defines now if uart or ethernet have to be tested. If yes, it checks the behavior of the enclosed firmwares. If not, simulation simply runs forever. rfajardo 4593d 06h /minsoc/
123 Renaming reg final to firmware_size. Final is a keyword for Verilator. rfajardo 4593d 10h /minsoc/

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