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Rev Log message Author Age Path
167 Ruben Diez fix to installation script problem in Windows:
minsoc-install.sh breaks if there are spaces in the PATH, which is rather common under Cygwin, as most Windows PCs have something like "C:\Program Files" in there.
rfajardo 2883d 19h /minsoc/
166 Turning on warnings for genera_bench.

Updating minsoc-install.sh to work better with directories and working around a missing inclusion of libftdi autotools. http://opencores.org/forum,OpenRISC,0,4685,1
rfajardo 2897d 18h /minsoc/
165 Board contribution: nexys2_1200 (Thanks to Johan Granath)

spartan3e_starter_kit_eth/minsoc_bench_defines.v: deprecated definition updated
rfajardo 2914d 19h /minsoc/
164 Updating width of minsoc_tc_top.v for Wishbone B3 compliance. This file has never worked. This solves at least the bug that some signals were not being routed through. rfajardo 2979d 12h /minsoc/
163 Adjusting internal initiator array widths. They were 1 bit too large. Thanks to R. Diez report.

These arrays abstract the complete initiator inputs. This way it is easier to route and arbiter using a single input.

Also removing 2 sequential delays. I didn't design them, so I can't tell if they were really useful/good.
rfajardo 2985d 19h /minsoc/
162 Tasks don't have parenthesis. This is only used for ports on modules. This was a mistake from my part. rfajardo 2991d 13h /minsoc/
161 Correcting configure parameters of adv_jtag_bridge on installation script. rfajardo 3004d 16h /minsoc/
160 Typo in minsoc-install.sh script. Adv_jtag_bridge was not configuring correctly. rfajardo 3004d 17h /minsoc/
159 Updated constraint file for de2_115 board. (Richard Hasha) rfajardo 3004d 17h /minsoc/
158 Adding de2_115_board port, thanks to Richard Hasha.

Support to JSP (JTAG Serial Port) working well. Also provided by Richard Hasha.

Different interconnect configurations per board are not straightforward on MinSoC. New added modules or definitions for addresses have to be carried over to other boards. Furthermore, extra modules can be shared among all projects. Thus, it is better to have this centralized:
-Removing interconnect configuration from minsoc_defines.v. There is an interconnect_defines.v file on rtl/verilog. The software counterpart is interconnect.h on sw/drivers.

Including a jsp firmware. It is basically the uart firmware but using JSP instead. Added to all board configure scripts to be compiled on configuration.

prj/srcs extended to include jsp and interconnec_defines.v.

spartan3e_starter_kit_eth lost UART (does not fit) and uses JSP instead now.
rfajardo 3006d 09h /minsoc/
157 Removed obsolete file; the changes in this version have been merged into
the mainline advanced debug system version 3.0 and higher.
nyawn 3012d 04h /minsoc/
156 Added hardware watchpoint indicators to debug unit break input, to allow
the debugger to break when a hardware watchpoint is triggered.
nyawn 3012d 04h /minsoc/
155 Decreased wait time, for faster simulations. nyawn 3012d 04h /minsoc/
154 Modified to use the new autotools support in the advanced debug system v3.0. nyawn 3012d 04h /minsoc/
153 Updating installation script to download minsoc from this branche, verilator, instead of rc-1.0. rfajardo 3044d 18h /minsoc/
152 Roll back to retrieve minsoc from branches/rc-1.0. rfajardo 3044d 18h /minsoc/
151 Creating tag release-1.0 from revision 150 of branches/rc-1.0. rfajardo 3044d 18h /minsoc/
150 Updating installation script to retrieve minsoc from tags/release-1.0. rfajardo 3044d 18h /minsoc/
149 Merging differences of release candidate 1.0 revision 140:148 with trunk. rfajardo 3044d 19h /minsoc/
148 Renaming minsoc_wave.lxt to minsoc_wave.lxt2 for correctness. rfajardo 3049d 15h /minsoc/

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