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31 Adaption to or1200_r3. It is still important to change or1200_defines.v:
-`define OR1200_BOOT_ADR 32'hf0000100 to `define OR1200_BOOT_ADR 32'h00000100
rfajardo 3424d 07h /minsoc/
30 minsoc SoC documentation had 2 small typo corrections. Performance penalty due to addition of register addresses was a wrong assumption. On project description "is composed by" -> "consists of". Thanks to Wojciech A. Koszek.

howto, at some places the howto did not tell the path from the files being talked about. I tried to always specify the path for every commented file.

Scripts for running the simulation called bash instead of sh. For compatibility reasons sh is now used, this should affect noone. Scripts do not use bash specific commands and generally every UNIX like computer has sh. Thanks again to Wojciech A. Koszek, who adapted that to port it to FreeBSD.
rfajardo 3467d 06h /minsoc/
29 Finishing the howto for Spartan3E Starter Kit with Ethernet. Last hint, change uart baudrate to 9600 to avoid the baudrate skew problem due to truncation.

Following the howto to implement Ethernet on Spartan3E Starter Kit will work flawlessly now.
rfajardo 3509d 05h /minsoc/
28 1) Period calculations through 1/freq on testbench use now a numerator definition in order to extract nano seconds of the divisions. Previously the number 1e9 was being repeatedly typed as numerator, now FREQ_NUM_FOR_NS is used.

2) There is a possibility of enabling the GENERIC_CLOCK_DIVISION for the testbench, so that you can test the outcome of different system clock inputs and internal clock adjustments. To do so, NO_CLOCK_DIVISION definition of minsoc_bench_defines.v has to be commented out.
-This also requested the initialization of the internal registers clk_int and clock_divisor of the minsoc_clock_manager.v, this is made by the testbench in case the NO_CLOCK_DIVISION definition is NOT defined.

3) Howto part of implementing Ethernet for the Spartan3E Starter Kit has been completely described. (Chapter 7, subitem 3)
rfajardo 3510d 01h /minsoc/
27 Simulation library fpga_memory_primitives.v had an issue with its lpm_ram_dq module, which did not output its data.

The data was being output to doq instead of q, the declared output. doq was also not defined anywhere else.

Icarus Verilog did not detect this, because Verilog-2001 allows internal wires to be used without being defined. To detect this errors, one can define "`default_nettype none". After doing this, Icarus Verilog detected that error and nothing else.

doq changed to q, error corrected.
rfajardo 3525d 01h /minsoc/
26 On version 34 of the Advanced Debug System the signal debug_tdo_o from the altera_virtual_jtag has changed to debug_tdo_i.

This commit adapts minsoc_top.v accordingly.
rfajardo 3534d 14h /minsoc/
25 Updated the howto document to adapt minsoc to a new update of the Advanced Debug System.
-Compilation of adv_jtag_bridge needs a Makefile adjustment.
-Simulation and Implementation have to remove a definition on the adbg_defines.v file.

Both adjustments simply removes the new JSP (JTAG Serial Port), which has been included in the new release of the Advanced Debug System.
rfajardo 3539d 06h /minsoc/
24 E-mail in the documentation has been corrected. rfajardo 3602d 19h /minsoc/
23 Paragraph minor changes, used in announcement and double checked. rfajardo 3606d 23h /minsoc/
22 Status progress and howto pdf documents were not commited, there now. rfajardo 3607d 00h /minsoc/
21 Including the first draft project documentation. How to and status progress docs are now separate from documentation. rfajardo 3607d 01h /minsoc/
20 minsoc_defines.v had a semicolon at the end of the two reset polarity definitions.

minsoc_top had a signal array for two different signals which was for backward compatibility. The compatible debugging module is so old that there is no reason for keeping it.

Documentation has been updated to better explain how to use the definitions files, minsoc_defines.v and or1200_defines.v. An example for Altera devices has been added too.
rfajardo 3614d 02h /minsoc/
19 Documentation update. How To: 7) Examples:
-Spartan 3E Starter Kit no Ethernet has been already tested and is known to work.
-Spartan 3E Starter Kit with Ethernet not yet.
-change of sw/support/orp.ld cannot be done by only commenting and uncommenting line, the instruction, documentation line, which said so has been removed.
-Further possibilities -> Further area optimization possibilities.
rfajardo 3645d 06h /minsoc/
18 Deprecated comments removed from the file listing files. rfajardo 3677d 06h /minsoc/
17 Ethernet testbench speed penalty solved. Now Ethernet of testbench and minsoc can be enabled by only uncommenting `define ETHERNET on minsoc_defines.v.

send_mac, get_mac and uart_send tasks have been included/improved. Also a testbench, which works for both included firmwares is added. (eth and uart)

If ETHERNET is defined for the SoC, both firmwares will complete successfully. If not, the eth firmware will stall when trying to access the Ethernet module.
rfajardo 3679d 01h /minsoc/
16 Further initialization improvement of non-used signals, setting interrupt signals to 0 if module is not used. rfajardo 3684d 05h /minsoc/
15 Including verified pinout for external spi flash on spartan3a dsp kit to its correspondent ucf constraint file. rfajardo 3684d 22h /minsoc/
14 Wishbone error signal of Ethernet core was not tied to ground if Ethernet was disabled. Solved now. rfajardo 3693d 05h /minsoc/
13 Updating spartan3e_starter_kit.ucf so that it does not deliver errors on mapping. Moreover it has been changed to off the shelf only have uart support. Ethernet support and generic JTAG can be added by uncommenting the corresponding lines. rfajardo 3694d 06h /minsoc/
12 1) spi_top.v:
-TX_NEGEDGE bug reported and recommended solution by Blaise Gassend. (Thank you)
2) minsoc howto extended to:
-synthesis of minsoc for Spartan3E Starter Kit with Ethernet
3) spartan3e_starter_kit.ucf changed:
-it had problems regarding pin definitions and IO logic types for mapping and place&route. Working flawless now.
rfajardo 3696d 21h /minsoc/

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