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Rev Log message Author Age Path
99 backend/altera_3c25_board/minsoc_defines.v: if GENERIC_FPGA selected, undefine ALTERA_FPGA and FPGA_FAMILY to avoid vendor specific code to flow into the simulation. If you don't do it, generate_bench fails. rfajardo 3257d 22h /minsoc/
98 Removing deprecated minsoc_top.qsf file. rfajardo 3257d 22h /minsoc/
97 As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. rfajardo 3257d 23h /minsoc/
96 Some files needed for Altera synthesis javieralso 3258d 09h /minsoc/
95 Makefile for Altera FPGAs fixed javieralso 3259d 12h /minsoc/
94 Fix bug in minsoc_top.prj for Altera synthesis javieralso 3261d 21h /minsoc/
93 Support for Altera synthesis. It needs some tune, but it works fine javieralso 3262d 00h /minsoc/
92 backend/spartan3e_starter_kit*: or1200_defines.v file was outdated and hindering synthesis. Probably it would be best if we used a patching system here. But for now, I copied the new files and made the necessary changes to fit the system into the target boards. rfajardo 3262d 22h /minsoc/
91 prj/scripts/: Changing scripts not to include multiple timescale.v files from different listed directories in the project definition file. Instead, now the internal loop which look for the file in different directories is broken when the first file is found. rfajardo 3262d 23h /minsoc/
90 After minsoc_top.prj update, make regenerated src and xst files. rfajardo 3263d 14h /minsoc/
89 minsoc_top.prj was splited into minsoc_top and minsoc_bench. minsoc_top still had directory entries of bench, they are gone now. rfajardo 3263d 14h /minsoc/
88 Project structure, Xilinx Makefiles and simulation working. rfajardo 3263d 15h /minsoc/
87 Synchronizing scripts to behave exactly the same. rfajardo 3263d 16h /minsoc/
86 Updating configure script messages. rfajardo 3263d 16h /minsoc/
85 Central project definition under prj. Synthesis and simulation take their project files from here. rfajardo 3263d 16h /minsoc/
84 syn/blackboxes/eth_top.v:
-module is now called ethmac instead of eth_top
-eth_defines.v is now called ethmac_defines.v
rfajardo 3264d 16h /minsoc/
83 minsoc-install.sh: bzip2 program was being used, but its existance on target system was not being verified. It is now. rfajardo 3275d 22h /minsoc/
82 minsoc-install.sh: problems with copying the GNU Toolchain from download to tools. We uncompress the GNU Toolchain now once again to tools during the installation part. rfajardo 3278d 21h /minsoc/
81 Installation script complete, nice text feedback, output logs and better execution order. rfajardo 3279d 08h /minsoc/
80 Establishing a better Makefile system for firmwares. rfajardo 3281d 20h /minsoc/

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