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132 ModelSim simulation, running top_module minsoc_bench_clock now, instead of minsoc_bench. rfajardo 3731d 15h /minsoc/branches
131 Renaming testbench modules. Adding to ifdefs without which the testbench generation can fail. rfajardo 3731d 15h /minsoc/branches
130 minsoc_bench.v: task test_eth has to be phased out together with the ETHERNET definition. If there is no ETHERNET, test_eth cannot be defined. rfajardo 3731d 18h /minsoc/branches
129 Removing bugs introduced when splitting clocks and reset.
1) NEGATIVE_RESET or POSITIVE_RESET were missing as definition on minsoc_bench_clock.v (include minsoc_defines.v).
2) wait for reset on minsoc_bench.v to assert design_ready
rfajardo 3732d 05h /minsoc/branches
128 Outsourcing clocks and reset generations from minsoc_bench.v to minsoc_bench_clock.v. rfajardo 3732d 06h /minsoc/branches
127 Removing redundant simulation output. rfajardo 3732d 12h /minsoc/branches
126 Updating information about simulation time for Ethernet test. rfajardo 3732d 12h /minsoc/branches
125 Adjusting testbench messages. Creating tasks for firmware tests. rfajardo 3732d 12h /minsoc/branches
124 Removing Verilog delays from minsoc_bench.v. minsoc_bench_defines.v defines now if uart or ethernet have to be tested. If yes, it checks the behavior of the enclosed firmwares. If not, simulation simply runs forever. rfajardo 3732d 14h /minsoc/branches
123 Renaming reg final to firmware_size. Final is a keyword for Verilator. rfajardo 3732d 19h /minsoc/branches
122 Renaming to rfajardo 3738d 08h /minsoc/branches
121 Asserting svn:executable properties of modelsim/*.bat scripts.

Including corrected patch for advanced debug system watchpoints under utils/setup. Configure script updated to use this instead of advanced debug system patches. This will remain so until the patch is corrected. The previous line still has the correct command.
rfajardo 3738d 10h /minsoc/branches
120 ethmac.prj: a file was missing rfajardo 3738d 12h /minsoc/branches
119 Tricking Subversion to accept bat files that are now executable. rfajardo 3738d 13h /minsoc/branches
118 Configure scripts for Xilinx devices updated. All of them require to update or1200_defines.v. The non-standard part uses now the variable $BOARD to print that this board require non-standard update of files. rfajardo 3738d 13h /minsoc/branches
117 spartan3e_starter_kit designs require DUALPORT from or1200_defines.v to be active instead of GENERIC. rfajardo 3738d 14h /minsoc/branches
116 Configure scripts were trying to copy/patch projects files before creating them. Ordering is correct now. rfajardo 3738d 14h /minsoc/branches
115 script dir aware. logging to script dir.
rfajardo 3738d 15h /minsoc/branches
114 Installation and Configuration scripts can be run out of any directory.
They assume they are going to process the files and directories found in the directory they are run from.
rfajardo 3738d 15h /minsoc/branches
113 &
-aware of location of script
-does not block on patch error

spartan3e_starter_kit & spartan3e_starter_kit_eth:
-or1200_defines.v updated

-src/blackboxes/or1200_top.v adjusted to or1200_rel1
-Makefile had a typo regarding altera vhdl files
rfajardo 3738d 15h /minsoc/branches

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