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Rev Log message Author Age Path
148 Renaming minsoc_wave.lxt to minsoc_wave.lxt2 for correctness. rfajardo 2934d 01h /minsoc/branches/
147 Updating minsoc_bench.v to correctly acquire uart data.

Uart drivers: when an end of line character was sent, the driver appended a carriage return to it. This is not necessary and has been removed.
-Eth and Uart firmwares also had a carriage return after the end of line, also removed.

Minsoc_bench_defines.v: Renaming VCD_OUTPUT define to WAVEFORM_OUTPUT

run_bench: selecting -lxt2 for waveform output format. This output format size is 10 times smaller than vcd.

minsoc-install.sh: lxt2 output format requires that Icarus Verilog be installed with zlib support. For that, we now check if zlib is supported on script run.
rfajardo 2934d 03h /minsoc/branches/
146 Importing 'Xilinx Microblaze Dev. Kit 1600E Edition' board configuration directory. ConX. 2934d 09h /minsoc/branches/
145 minsoc_bench_core.v and minsoc_bench_clock.v left only on verilator branche. It will develop there until it is ported for inclusion into trunk. RC-1.0 is now clean of it. rfajardo 2934d 18h /minsoc/branches/
143 Compiling firmwares in board configuration scripts instead of on global minsoc setup. rfajardo 2935d 04h /minsoc/branches/
140 Including required modules for verilator simulation. rfajardo 2935d 05h /minsoc/branches/
139 Creating a verilator branche. rfajardo 2935d 05h /minsoc/branches/
138 DIR_TO_INSTALL creation using wizard ConX. 2935d 18h /minsoc/branches/
137 Removing uncomplete support for ml509 and not working support for spartan3e_starter_kit_eth (area constraint cannot be reached). rfajardo 2936d 05h /minsoc/branches/
136 Installation on Ubuntu-11.10 has shown that a binary called makeinfo is required to install GDB. This binary can be installed on Ubuntu by installing the package texinfo. rfajardo 2943d 00h /minsoc/branches/
134 run_sim.bat for ModelSim updated to acquire the firmware_size for command line input when running the testbench. rfajardo 2950d 04h /minsoc/branches/
133 Roll back minsoc_bench.v to timed simulation. Merge minsoc_bench_core and minsoc_bench_clock again.

Applying Rubén Diez patch to avoid warnings on firmware load for simulation.
rfajardo 2950d 05h /minsoc/branches/
132 ModelSim simulation, running top_module minsoc_bench_clock now, instead of minsoc_bench. rfajardo 2954d 01h /minsoc/branches/
131 Renaming testbench modules. Adding to ifdefs without which the testbench generation can fail. rfajardo 2954d 01h /minsoc/branches/
130 minsoc_bench.v: task test_eth has to be phased out together with the ETHERNET definition. If there is no ETHERNET, test_eth cannot be defined. rfajardo 2954d 04h /minsoc/branches/
129 Removing bugs introduced when splitting clocks and reset.
1) NEGATIVE_RESET or POSITIVE_RESET were missing as definition on minsoc_bench_clock.v (include minsoc_defines.v).
2) wait for reset on minsoc_bench.v to assert design_ready
rfajardo 2954d 15h /minsoc/branches/
128 Outsourcing clocks and reset generations from minsoc_bench.v to minsoc_bench_clock.v. rfajardo 2954d 16h /minsoc/branches/
127 Removing redundant simulation output. rfajardo 2954d 22h /minsoc/branches/
126 Updating information about simulation time for Ethernet test. rfajardo 2954d 22h /minsoc/branches/
125 Adjusting testbench messages. Creating tasks for firmware tests. rfajardo 2954d 22h /minsoc/branches/

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