OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] - Rev 153

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
127 Removing redundant simulation output. rfajardo 4564d 06h /minsoc/branches
126 Updating information about simulation time for Ethernet test. rfajardo 4564d 06h /minsoc/branches
125 Adjusting testbench messages. Creating tasks for firmware tests. rfajardo 4564d 06h /minsoc/branches
124 Removing Verilog delays from minsoc_bench.v. minsoc_bench_defines.v defines now if uart or ethernet have to be tested. If yes, it checks the behavior of the enclosed firmwares. If not, simulation simply runs forever. rfajardo 4564d 08h /minsoc/branches
123 Renaming reg final to firmware_size. Final is a keyword for Verilator. rfajardo 4564d 13h /minsoc/branches
122 Renaming minsoc-configure.sh to minsoc-setup.sh. rfajardo 4570d 02h /minsoc/branches
121 Asserting svn:executable properties of modelsim/*.bat scripts.

Including corrected patch for advanced debug system watchpoints under utils/setup. Configure script updated to use this instead of advanced debug system patches. This will remain so until the patch is corrected. The previous line still has the correct command.
rfajardo 4570d 04h /minsoc/branches
120 ethmac.prj: a file was missing rfajardo 4570d 06h /minsoc/branches
119 Tricking Subversion to accept bat files that are now executable. rfajardo 4570d 07h /minsoc/branches
118 Configure scripts for Xilinx devices updated. All of them require to update or1200_defines.v. The non-standard part uses now the variable $BOARD to print that this board require non-standard update of files. rfajardo 4570d 07h /minsoc/branches

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.