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Rev Log message Author Age Path
127 Removing redundant simulation output. rfajardo 4168d 17h /minsoc/branches/
126 Updating information about simulation time for Ethernet test. rfajardo 4168d 17h /minsoc/branches/
125 Adjusting testbench messages. Creating tasks for firmware tests. rfajardo 4168d 17h /minsoc/branches/
124 Removing Verilog delays from minsoc_bench.v. minsoc_bench_defines.v defines now if uart or ethernet have to be tested. If yes, it checks the behavior of the enclosed firmwares. If not, simulation simply runs forever. rfajardo 4168d 19h /minsoc/branches/
123 Renaming reg final to firmware_size. Final is a keyword for Verilator. rfajardo 4169d 00h /minsoc/branches/
122 Renaming minsoc-configure.sh to minsoc-setup.sh. rfajardo 4174d 14h /minsoc/branches/
121 Asserting svn:executable properties of modelsim/*.bat scripts.

Including corrected patch for advanced debug system watchpoints under utils/setup. Configure script updated to use this instead of advanced debug system patches. This will remain so until the patch is corrected. The previous line still has the correct command.
rfajardo 4174d 15h /minsoc/branches/
120 ethmac.prj: a file was missing rfajardo 4174d 18h /minsoc/branches/
119 Tricking Subversion to accept bat files that are now executable. rfajardo 4174d 18h /minsoc/branches/
118 Configure scripts for Xilinx devices updated. All of them require to update or1200_defines.v. The non-standard part uses now the variable $BOARD to print that this board require non-standard update of files. rfajardo 4174d 19h /minsoc/branches/

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