Rev |
Log message |
Author |
Age |
Path |
103 |
But the file is called gdb-6.8a.tar.bz2, so tar must be run on that name. |
rfajardo |
4590d 18h |
/minsoc/branches/rc-1.0 |
102 |
GNU GDB FTP has renamed gdb-6.8 package to gdb-6.8a package. Uncompressed it remains gdb-6.8, so no other changes to script are necessary. |
rfajardo |
4590d 18h |
/minsoc/branches/rc-1.0 |
101 |
Documentation, wiki's address updated. |
rfajardo |
4616d 06h |
/minsoc/branches/rc-1.0 |
100 |
syn/altera/minsoc_top.qsf: I thought this file was being generated now as project file description. But it is merely a synthesis configuration file and must be here. File re-added. |
rfajardo |
4625d 04h |
/minsoc/branches/rc-1.0 |
99 |
backend/altera_3c25_board/minsoc_defines.v: if GENERIC_FPGA selected, undefine ALTERA_FPGA and FPGA_FAMILY to avoid vendor specific code to flow into the simulation. If you don't do it, generate_bench fails. |
rfajardo |
4625d 04h |
/minsoc/branches/rc-1.0 |
98 |
Removing deprecated minsoc_top.qsf file. |
rfajardo |
4625d 04h |
/minsoc/branches/rc-1.0 |
97 |
As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. |
rfajardo |
4625d 05h |
/minsoc/branches/rc-1.0 |
96 |
Some files needed for Altera synthesis |
javieralso |
4625d 15h |
/minsoc/branches/rc-1.0 |
95 |
Makefile for Altera FPGAs fixed |
javieralso |
4626d 18h |
/minsoc/branches/rc-1.0 |
94 |
Fix bug in minsoc_top.prj for Altera synthesis |
javieralso |
4629d 03h |
/minsoc/branches/rc-1.0 |
93 |
Support for Altera synthesis. It needs some tune, but it works fine |
javieralso |
4629d 06h |
/minsoc/branches/rc-1.0 |
92 |
backend/spartan3e_starter_kit*: or1200_defines.v file was outdated and hindering synthesis. Probably it would be best if we used a patching system here. But for now, I copied the new files and made the necessary changes to fit the system into the target boards. |
rfajardo |
4630d 04h |
/minsoc/branches/rc-1.0 |
91 |
prj/scripts/: Changing scripts not to include multiple timescale.v files from different listed directories in the project definition file. Instead, now the internal loop which look for the file in different directories is broken when the first file is found. |
rfajardo |
4630d 05h |
/minsoc/branches/rc-1.0 |
90 |
After minsoc_top.prj update, make regenerated src and xst files. |
rfajardo |
4630d 20h |
/minsoc/branches/rc-1.0 |
89 |
minsoc_top.prj was splited into minsoc_top and minsoc_bench. minsoc_top still had directory entries of bench, they are gone now. |
rfajardo |
4630d 20h |
/minsoc/branches/rc-1.0 |
88 |
Project structure, Xilinx Makefiles and simulation working. |
rfajardo |
4630d 21h |
/minsoc/branches/rc-1.0 |
87 |
Synchronizing scripts to behave exactly the same. |
rfajardo |
4630d 22h |
/minsoc/branches/rc-1.0 |
86 |
Updating configure script messages. |
rfajardo |
4630d 22h |
/minsoc/branches/rc-1.0 |
85 |
Central project definition under prj. Synthesis and simulation take their project files from here. |
rfajardo |
4630d 22h |
/minsoc/branches/rc-1.0 |
84 |
syn/blackboxes/eth_top.v:
-module is now called ethmac instead of eth_top
-eth_defines.v is now called ethmac_defines.v |
rfajardo |
4631d 23h |
/minsoc/branches/rc-1.0 |
83 |
minsoc-install.sh: bzip2 program was being used, but its existance on target system was not being verified. It is now. |
rfajardo |
4643d 04h |
/minsoc/branches/rc-1.0 |
82 |
minsoc-install.sh: problems with copying the GNU Toolchain from download to tools. We uncompress the GNU Toolchain now once again to tools during the installation part. |
rfajardo |
4646d 03h |
/minsoc/branches/rc-1.0 |
81 |
Installation script complete, nice text feedback, output logs and better execution order. |
rfajardo |
4646d 14h |
/minsoc/branches/rc-1.0 |
80 |
Establishing a better Makefile system for firmwares. |
rfajardo |
4649d 02h |
/minsoc/branches/rc-1.0 |
79 |
minsoc-install.sh: rpath corrected.
required-cygwin-tools: updated |
rfajardo |
4649d 19h |
/minsoc/branches/rc-1.0 |
78 |
minsoc-install.sh: Advanced JTAG bridge compilation needs to know where the dynamic libraries are on runtime. Patching (sed) the Makefile to compile it with the rpath to the libraries (libusb/libftdi). |
rfajardo |
4649d 19h |
/minsoc/branches/rc-1.0 |
77 |
New tool requirements for installing Icarus Verilog. |
rfajardo |
4649d 20h |
/minsoc/branches/rc-1.0 |
76 |
Including a script allowing the installation of MinSoC and all its required tools.
It should be working for all Linuxes and Cygwin. |
rfajardo |
4649d 20h |
/minsoc/branches/rc-1.0 |
75 |
Adapting minsoc_top.v and minsoc_verilog_files.txt to new names for top modules and define file of ethmac ip core. |
rfajardo |
4656d 20h |
/minsoc/branches/rc-1.0 |
74 |
or1200.h includes a CLABLE macro which uses __USER_LABEL_PREFIX__(from compiler defined macro) to find out if we need the underscore as prefix to reference C functions (its assembly labels) or not.
except.S and reset.S use CLABLE to call externally defined C functions.
This should avoid problems compiling firmware with old or new toolchain.
support/common.mk updated, reset-nocache.o and reset-icdc.o are dependent on or1200.h |
rfajardo |
4749d 18h |
/minsoc/branches/rc-1.0 |