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Rev Log message Author Age Path
96 Some files needed for Altera synthesis javieralso 4658d 18h /minsoc/branches/rc-1.0/
95 Makefile for Altera FPGAs fixed javieralso 4659d 21h /minsoc/branches/rc-1.0/
94 Fix bug in minsoc_top.prj for Altera synthesis javieralso 4662d 06h /minsoc/branches/rc-1.0/
93 Support for Altera synthesis. It needs some tune, but it works fine javieralso 4662d 09h /minsoc/branches/rc-1.0/
92 backend/spartan3e_starter_kit*: or1200_defines.v file was outdated and hindering synthesis. Probably it would be best if we used a patching system here. But for now, I copied the new files and made the necessary changes to fit the system into the target boards. rfajardo 4663d 07h /minsoc/branches/rc-1.0/
91 prj/scripts/: Changing scripts not to include multiple timescale.v files from different listed directories in the project definition file. Instead, now the internal loop which look for the file in different directories is broken when the first file is found. rfajardo 4663d 07h /minsoc/branches/rc-1.0/
90 After minsoc_top.prj update, make regenerated src and xst files. rfajardo 4663d 23h /minsoc/branches/rc-1.0/
89 minsoc_top.prj was splited into minsoc_top and minsoc_bench. minsoc_top still had directory entries of bench, they are gone now. rfajardo 4663d 23h /minsoc/branches/rc-1.0/
88 Project structure, Xilinx Makefiles and simulation working. rfajardo 4663d 23h /minsoc/branches/rc-1.0/
87 Synchronizing scripts to behave exactly the same. rfajardo 4664d 00h /minsoc/branches/rc-1.0/

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