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[/] [minsoc/] [branches/] [rc-1.0/] - Rev 132

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132 ModelSim simulation, running top_module minsoc_bench_clock now, instead of minsoc_bench. rfajardo 4495d 11h /minsoc/branches/rc-1.0/
131 Renaming testbench modules. Adding to ifdefs without which the testbench generation can fail. rfajardo 4495d 11h /minsoc/branches/rc-1.0/
130 minsoc_bench.v: task test_eth has to be phased out together with the ETHERNET definition. If there is no ETHERNET, test_eth cannot be defined. rfajardo 4495d 14h /minsoc/branches/rc-1.0/
129 Removing bugs introduced when splitting clocks and reset.
1) NEGATIVE_RESET or POSITIVE_RESET were missing as definition on minsoc_bench_clock.v (include minsoc_defines.v).
2) wait for reset on minsoc_bench.v to assert design_ready
rfajardo 4496d 01h /minsoc/branches/rc-1.0/
128 Outsourcing clocks and reset generations from minsoc_bench.v to minsoc_bench_clock.v. rfajardo 4496d 02h /minsoc/branches/rc-1.0/
127 Removing redundant simulation output. rfajardo 4496d 08h /minsoc/branches/rc-1.0/
126 Updating information about simulation time for Ethernet test. rfajardo 4496d 08h /minsoc/branches/rc-1.0/
125 Adjusting testbench messages. Creating tasks for firmware tests. rfajardo 4496d 08h /minsoc/branches/rc-1.0/
124 Removing Verilog delays from minsoc_bench.v. minsoc_bench_defines.v defines now if uart or ethernet have to be tested. If yes, it checks the behavior of the enclosed firmwares. If not, simulation simply runs forever. rfajardo 4496d 10h /minsoc/branches/rc-1.0/
123 Renaming reg final to firmware_size. Final is a keyword for Verilator. rfajardo 4496d 15h /minsoc/branches/rc-1.0/
122 Renaming minsoc-configure.sh to minsoc-setup.sh. rfajardo 4502d 04h /minsoc/branches/rc-1.0/
121 Asserting svn:executable properties of modelsim/*.bat scripts.

Including corrected patch for advanced debug system watchpoints under utils/setup. Configure script updated to use this instead of advanced debug system patches. This will remain so until the patch is corrected. The previous line still has the correct command.
rfajardo 4502d 06h /minsoc/branches/rc-1.0/
120 ethmac.prj: a file was missing rfajardo 4502d 09h /minsoc/branches/rc-1.0/
119 Tricking Subversion to accept bat files that are now executable. rfajardo 4502d 09h /minsoc/branches/rc-1.0/
118 Configure scripts for Xilinx devices updated. All of them require to update or1200_defines.v. The non-standard part uses now the variable $BOARD to print that this board require non-standard update of files. rfajardo 4502d 09h /minsoc/branches/rc-1.0/
117 spartan3e_starter_kit designs require DUALPORT from or1200_defines.v to be active instead of GENERIC. rfajardo 4502d 10h /minsoc/branches/rc-1.0/
116 Configure scripts were trying to copy/patch projects files before creating them. Ordering is correct now. rfajardo 4502d 11h /minsoc/branches/rc-1.0/
115 configure.sh script dir aware.
minsoc-install.sh logging to script dir.
rfajardo 4502d 11h /minsoc/branches/rc-1.0/
114 Installation and Configuration scripts can be run out of any directory.
They assume they are going to process the files and directories found in the directory they are run from.
rfajardo 4502d 11h /minsoc/branches/rc-1.0/
113 minsoc-install.sh & minsoc-configure.sh:
-aware of location of configure.sh script
configure.sh:
-does not block on patch error

spartan3e_starter_kit & spartan3e_starter_kit_eth:
-or1200_defines.v updated

prj:
-src/blackboxes/or1200_top.v adjusted to or1200_rel1
-Makefile had a typo regarding altera vhdl files
rfajardo 4502d 12h /minsoc/branches/rc-1.0/

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