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Rev Log message Author Age Path
109 Creating a branche for release candidate 1.0. rfajardo 3289d 04h /minsoc/branches/rc-1.0/backend/
105 Updating configure scripts to copy Windows synthesis launch script setup.bat from either minsoc/syn/altera or minsoc/syn/xilinx to minsoc/syn. rfajardo 3289d 15h /minsoc/trunk/backend/
99 backend/altera_3c25_board/minsoc_defines.v: if GENERIC_FPGA selected, undefine ALTERA_FPGA and FPGA_FAMILY to avoid vendor specific code to flow into the simulation. If you don't do it, generate_bench fails. rfajardo 3333d 15h /minsoc/trunk/backend/
97 As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. rfajardo 3333d 15h /minsoc/trunk/backend/
96 Some files needed for Altera synthesis javieralso 3334d 02h /minsoc/trunk/backend/
95 Makefile for Altera FPGAs fixed javieralso 3335d 05h /minsoc/trunk/backend/
93 Support for Altera synthesis. It needs some tune, but it works fine javieralso 3337d 17h /minsoc/trunk/backend/
92 backend/spartan3e_starter_kit*: or1200_defines.v file was outdated and hindering synthesis. Probably it would be best if we used a patching system here. But for now, I copied the new files and made the necessary changes to fit the system into the target boards. rfajardo 3338d 15h /minsoc/trunk/backend/
88 Project structure, Xilinx Makefiles and simulation working. rfajardo 3339d 07h /minsoc/trunk/backend/
87 Synchronizing scripts to behave exactly the same. rfajardo 3339d 09h /minsoc/trunk/backend/
86 Updating configure script messages. rfajardo 3339d 09h /minsoc/trunk/backend/
85 Central project definition under prj. Synthesis and simulation take their project files from here. rfajardo 3339d 09h /minsoc/trunk/backend/
80 Establishing a better Makefile system for firmwares. rfajardo 3357d 13h /minsoc/trunk/backend/
70 Including a global timescale under minsoc/rtl/verilog to control simulation. It is under the implementation because the implementation files include it.

Removing timescale definition of minsoc_bench_defines.v files.

Creating a modelsim simulation directory. Everything is working under Linux. For Windows, has to be changed:
-pli ../../bench/verilog/vpi/
-pli ../../bench/verilog/vpi/jp-io-vpi.dll

These files have to be compiled/copied from minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/modelsim_platform to minsoc/bench/verilog/vpi.
rfajardo 3458d 14h /minsoc/trunk/backend/
69 backend update:
Both files should now be under minsoc/backend to proper system functionality.
backend subdirectories have been given those files. Configure script updated accordingly.

They are searched there from system scripts and Makefiles.
-sim/bin/minsoc_verilog_files.txt has the files for Icarus Verilog, minsoc_bench_defines.v is now referenced from backend directory.
-sw/support/ now references to inside backend.

-It is the system configuration for Spartan 3E Starter Kit with Ethernet.
rfajardo 3463d 06h /minsoc/trunk/backend/
68 Still one configuration mismatch on minsoc_defines.v:
-orp.ld is defined accordingly
rfajardo 3465d 10h /minsoc/trunk/backend/
67 Constraint file for backend spartan3a_dsp_kit.ucf was configured to include the STARTUP module.

This module is not enabled under the respective minsoc_defines.v. Thus, its pins had to be commented out.
rfajardo 3465d 10h /minsoc/trunk/backend/
66 spartan3e_starter_kit requires special configuration of or1200_r3.

For that, configure script was specially adapted and that is reported on script execution.

For release-1.0 of MinSoC this should not be required, because or1200_r1 already has the
required configuration.
rfajardo 3465d 11h /minsoc/trunk/backend/
65 Files missing in the last commit.
sw: eth, uart and driver Makefiles
rfajardo 3465d 12h /minsoc/trunk/backend/
64 firmware makefiles:
-every firmware makefile has now complete dependency. This also includes dependency on files under minsoc/backend (target specific files). That means, that if some target specific header changes, the support library dependent on it will be compiled. That will always happen, even if you compile the uart firmware. In other words, if you want to use uart firmware, you can always simply compile uart by issuing make all. If anything has changed, backend files, support library, drivers, it will update everything for you.
-TODO: dependency can be automatic created by using make together with gcc. Use it instead of declaring all dependencies manually.

Makefile system for synthesis:
-the dependency for every implementation step has been checked and is working fine.
-Makefile plus support files have been moved to minsoc/syn/src
-make usage is still under syn through files generated by backend bashscripts
-files under backend are target specific files used for the system to work
-firmware compilation
-system simulation
-system implementation
-This directory is populated by visiting one of its subdirectories and typing ./configure

-working on FPGA

-has to be tested

-missing files have to be copied and adapted, configure script has to be copied and adapted

-include files necessary for firmware compilation and system configuration
-it does not include files for synthesis and is not synthesizable
rfajardo 3465d 13h /minsoc/trunk/backend/

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