| Rev |
Log message |
Author |
Age |
Path |
| 118 |
Configure scripts for Xilinx devices updated. All of them require to update or1200_defines.v. The non-standard part uses now the variable $BOARD to print that this board require non-standard update of files. |
rfajardo |
4728d 10h |
/minsoc/branches/rc-1.0/backend/ |
| 117 |
spartan3e_starter_kit designs require DUALPORT from or1200_defines.v to be active instead of GENERIC. |
rfajardo |
4728d 11h |
/minsoc/branches/rc-1.0/backend/ |
| 116 |
Configure scripts were trying to copy/patch projects files before creating them. Ordering is correct now. |
rfajardo |
4728d 11h |
/minsoc/branches/rc-1.0/backend/ |
| 113 |
minsoc-install.sh & minsoc-configure.sh:
-aware of location of configure.sh script
configure.sh:
-does not block on patch error
spartan3e_starter_kit & spartan3e_starter_kit_eth:
-or1200_defines.v updated
prj:
-src/blackboxes/or1200_top.v adjusted to or1200_rel1
-Makefile had a typo regarding altera vhdl files |
rfajardo |
4728d 13h |
/minsoc/branches/rc-1.0/backend/ |
| 110 |
Fixing several minor issues with the system:
-minsoc-install splitted into installation and configuration
-minsoc-configure.sh can be used to configure a fresh checked out system
-configure script used by both minsoc-configure.sh and minsoc-install.sh to configure
-rtl/verilog: svn externals fixed
-or1200 rolled back to release-1.0
-prj/scripts:
-Makefile has been used by simulation to differentiate project definition of vhdl and verilog files
-Altera was differentiating it in script
-now there are two scripts, one for vhdl and another for verilog. The differentiation occurs in Makefile as for simulation.
-altera_3c25_board/configure scripts had to be updated, vprj and vhdprj file extensions used to differentiate Verilog and VHDL project files.
-prj/src: or1200_top.prj downdated to definition of or1200_v1 |
rfajardo |
4729d 05h |
/minsoc/branches/rc-1.0/backend/ |
| 109 |
Creating a branche for release candidate 1.0. |
rfajardo |
4729d 07h |
/minsoc/branches/rc-1.0/backend/ |
| 105 |
Updating configure scripts to copy Windows synthesis launch script setup.bat from either minsoc/syn/altera or minsoc/syn/xilinx to minsoc/syn. |
rfajardo |
4729d 17h |
/minsoc/trunk/backend/ |
| 99 |
backend/altera_3c25_board/minsoc_defines.v: if GENERIC_FPGA selected, undefine ALTERA_FPGA and FPGA_FAMILY to avoid vendor specific code to flow into the simulation. If you don't do it, generate_bench fails. |
rfajardo |
4773d 17h |
/minsoc/trunk/backend/ |
| 97 |
As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. |
rfajardo |
4773d 17h |
/minsoc/trunk/backend/ |
| 96 |
Some files needed for Altera synthesis |
javieralso |
4774d 04h |
/minsoc/trunk/backend/ |
| 95 |
Makefile for Altera FPGAs fixed |
javieralso |
4775d 07h |
/minsoc/trunk/backend/ |
| 93 |
Support for Altera synthesis. It needs some tune, but it works fine |
javieralso |
4777d 19h |
/minsoc/trunk/backend/ |
| 92 |
backend/spartan3e_starter_kit*: or1200_defines.v file was outdated and hindering synthesis. Probably it would be best if we used a patching system here. But for now, I copied the new files and made the necessary changes to fit the system into the target boards. |
rfajardo |
4778d 17h |
/minsoc/trunk/backend/ |
| 88 |
Project structure, Xilinx Makefiles and simulation working. |
rfajardo |
4779d 09h |
/minsoc/trunk/backend/ |
| 87 |
Synchronizing scripts to behave exactly the same. |
rfajardo |
4779d 11h |
/minsoc/trunk/backend/ |
| 86 |
Updating configure script messages. |
rfajardo |
4779d 11h |
/minsoc/trunk/backend/ |
| 85 |
Central project definition under prj. Synthesis and simulation take their project files from here. |
rfajardo |
4779d 11h |
/minsoc/trunk/backend/ |
| 80 |
Establishing a better Makefile system for firmwares. |
rfajardo |
4797d 15h |
/minsoc/trunk/backend/ |
| 70 |
Including a global timescale under minsoc/rtl/verilog to control simulation. It is under the implementation because the implementation files include it.
Removing timescale definition of minsoc_bench_defines.v files.
Creating a modelsim simulation directory. Everything is working under Linux. For Windows, run_sim.sh has to be changed:
-pli ../../bench/verilog/vpi/jp-io-vpi.so
to:
-pli ../../bench/verilog/vpi/jp-io-vpi.dll
These files have to be compiled/copied from minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/modelsim_platform to minsoc/bench/verilog/vpi. |
rfajardo |
4898d 16h |
/minsoc/trunk/backend/ |
| 69 |
backend update:
-minsoc_bench_defines.v
-gcc-opt.mk
Both files should now be under minsoc/backend to proper system functionality.
backend subdirectories have been given those files. Configure script updated accordingly.
They are searched there from system scripts and Makefiles.
-sim/bin/minsoc_verilog_files.txt has the files for Icarus Verilog, minsoc_bench_defines.v is now referenced from backend directory.
-sw/support/Makefile.inc now references to gcc-opt.mk inside backend.
backend/spartan3e_starter_kit_eth:
-It is the system configuration for Spartan 3E Starter Kit with Ethernet. |
rfajardo |
4903d 08h |
/minsoc/trunk/backend/ |
