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[/] [minsoc/] [branches/] [rc-1.0/] [backend/] [altera_3c25_board/] [minsoc_bench_defines.v] - Rev 124

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124 Removing Verilog delays from minsoc_bench.v. minsoc_bench_defines.v defines now if uart or ethernet have to be tested. If yes, it checks the behavior of the enclosed firmwares. If not, simulation simply runs forever. rfajardo 3278d 06h /minsoc/branches/rc-1.0/backend/altera_3c25_board/minsoc_bench_defines.v
109 Creating a branche for release candidate 1.0. rfajardo 3285d 01h /minsoc/branches/rc-1.0/backend/altera_3c25_board/minsoc_bench_defines.v
93 Support for Altera synthesis. It needs some tune, but it works fine javieralso 3333d 13h /minsoc/branches/rc-1.0/backend/altera_3c25_board/minsoc_bench_defines.v

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