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[/] [minsoc/] [branches/] [rc-1.0/] [backend/] [spartan3a_dsp_kit/] [minsoc_bench_defines.v] - Rev 124


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124 Removing Verilog delays from minsoc_bench.v. minsoc_bench_defines.v defines now if uart or ethernet have to be tested. If yes, it checks the behavior of the enclosed firmwares. If not, simulation simply runs forever. rfajardo 3278d 07h /minsoc/branches/rc-1.0/backend/spartan3a_dsp_kit/minsoc_bench_defines.v
109 Creating a branche for release candidate 1.0. rfajardo 3285d 02h /minsoc/branches/rc-1.0/backend/spartan3a_dsp_kit/minsoc_bench_defines.v
70 Including a global timescale under minsoc/rtl/verilog to control simulation. It is under the implementation because the implementation files include it.

Removing timescale definition of minsoc_bench_defines.v files.

Creating a modelsim simulation directory. Everything is working under Linux. For Windows, has to be changed:
-pli ../../bench/verilog/vpi/
-pli ../../bench/verilog/vpi/jp-io-vpi.dll

These files have to be compiled/copied from minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/modelsim_platform to minsoc/bench/verilog/vpi.
rfajardo 3454d 12h /minsoc/branches/rc-1.0/backend/spartan3a_dsp_kit/minsoc_bench_defines.v
69 backend update:
Both files should now be under minsoc/backend to proper system functionality.
backend subdirectories have been given those files. Configure script updated accordingly.

They are searched there from system scripts and Makefiles.
-sim/bin/minsoc_verilog_files.txt has the files for Icarus Verilog, minsoc_bench_defines.v is now referenced from backend directory.
-sw/support/ now references to inside backend.

-It is the system configuration for Spartan 3E Starter Kit with Ethernet.
rfajardo 3459d 04h /minsoc/branches/rc-1.0/backend/spartan3a_dsp_kit/minsoc_bench_defines.v

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