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124 Removing Verilog delays from minsoc_bench.v. minsoc_bench_defines.v defines now if uart or ethernet have to be tested. If yes, it checks the behavior of the enclosed firmwares. If not, simulation simply runs forever. rfajardo 3312d 06h /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit/
118 Configure scripts for Xilinx devices updated. All of them require to update or1200_defines.v. The non-standard part uses now the variable $BOARD to print that this board require non-standard update of files. rfajardo 3318d 05h /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit/
117 spartan3e_starter_kit designs require DUALPORT from or1200_defines.v to be active instead of GENERIC. rfajardo 3318d 06h /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit/
116 Configure scripts were trying to copy/patch projects files before creating them. Ordering is correct now. rfajardo 3318d 06h /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit/
113 minsoc-install.sh & minsoc-configure.sh:
-aware of location of configure.sh script
configure.sh:
-does not block on patch error

spartan3e_starter_kit & spartan3e_starter_kit_eth:
-or1200_defines.v updated

prj:
-src/blackboxes/or1200_top.v adjusted to or1200_rel1
-Makefile had a typo regarding altera vhdl files
rfajardo 3318d 07h /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit/
109 Creating a branche for release candidate 1.0. rfajardo 3319d 01h /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit/
105 Updating configure scripts to copy Windows synthesis launch script setup.bat from either minsoc/syn/altera or minsoc/syn/xilinx to minsoc/syn. rfajardo 3319d 12h /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit/
97 As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. rfajardo 3363d 12h /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit/
92 backend/spartan3e_starter_kit*: or1200_defines.v file was outdated and hindering synthesis. Probably it would be best if we used a patching system here. But for now, I copied the new files and made the necessary changes to fit the system into the target boards. rfajardo 3368d 11h /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit/
88 Project structure, Xilinx Makefiles and simulation working. rfajardo 3369d 04h /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit/
87 Synchronizing scripts to behave exactly the same. rfajardo 3369d 05h /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit/
86 Updating configure script messages. rfajardo 3369d 05h /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit/
85 Central project definition under prj. Synthesis and simulation take their project files from here. rfajardo 3369d 06h /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit/
80 Establishing a better Makefile system for firmwares. rfajardo 3387d 10h /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit/
70 Including a global timescale under minsoc/rtl/verilog to control simulation. It is under the implementation because the implementation files include it.

Removing timescale definition of minsoc_bench_defines.v files.

Creating a modelsim simulation directory. Everything is working under Linux. For Windows, run_sim.sh has to be changed:
-pli ../../bench/verilog/vpi/jp-io-vpi.so
to:
-pli ../../bench/verilog/vpi/jp-io-vpi.dll

These files have to be compiled/copied from minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/modelsim_platform to minsoc/bench/verilog/vpi.
rfajardo 3488d 11h /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit/
69 backend update:
-minsoc_bench_defines.v
-gcc-opt.mk
Both files should now be under minsoc/backend to proper system functionality.
backend subdirectories have been given those files. Configure script updated accordingly.

They are searched there from system scripts and Makefiles.
-sim/bin/minsoc_verilog_files.txt has the files for Icarus Verilog, minsoc_bench_defines.v is now referenced from backend directory.
-sw/support/Makefile.inc now references to gcc-opt.mk inside backend.

backend/spartan3e_starter_kit_eth:
-It is the system configuration for Spartan 3E Starter Kit with Ethernet.
rfajardo 3493d 03h /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit/
66 spartan3e_starter_kit requires special configuration of or1200_r3.

For that, configure script was specially adapted and that is reported on script execution.

For release-1.0 of MinSoC this should not be required, because or1200_r1 already has the
required configuration.
rfajardo 3495d 07h /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit/
64 firmware makefiles:
-every firmware makefile has now complete dependency. This also includes dependency on files under minsoc/backend (target specific files). That means, that if some target specific header changes, the support library dependent on it will be compiled. That will always happen, even if you compile the uart firmware. In other words, if you want to use uart firmware, you can always simply compile uart by issuing make all. If anything has changed, backend files, support library, drivers, it will update everything for you.
-TODO: dependency can be automatic created by using make together with gcc. Use it instead of declaring all dependencies manually.

Makefile system for synthesis:
-the dependency for every implementation step has been checked and is working fine.
-Makefile plus support files have been moved to minsoc/syn/src
-make usage is still under syn through files generated by backend bashscripts
Backend:
-files under backend are target specific files used for the system to work
-firmware compilation
-system simulation
-system implementation
-This directory is populated by visiting one of its subdirectories and typing ./configure

backend/spartan3a_dsp_kit:
-working on FPGA

backend/spartan3e_starter_kit:
-has to be tested

backend/ml509:
-missing files have to be copied and adapted, configure script has to be copied and adapted

backend/std:
-include files necessary for firmware compilation and system configuration
-it does not include files for synthesis and is not synthesizable
rfajardo 3495d 10h /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit/

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