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116 Configure scripts were trying to copy/patch projects files before creating them. Ordering is correct now. rfajardo 4501d 10h /minsoc/branches/rc-1.0/backend/std/configure
109 Creating a branche for release candidate 1.0. rfajardo 4502d 05h /minsoc/branches/rc-1.0/backend/std/configure
105 Updating configure scripts to copy Windows synthesis launch script setup.bat from either minsoc/syn/altera or minsoc/syn/xilinx to minsoc/syn. rfajardo 4502d 16h /minsoc/branches/rc-1.0/backend/std/configure
97 As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. rfajardo 4546d 16h /minsoc/branches/rc-1.0/backend/std/configure
87 Synchronizing scripts to behave exactly the same. rfajardo 4552d 09h /minsoc/branches/rc-1.0/backend/std/configure
85 Central project definition under prj. Synthesis and simulation take their project files from here. rfajardo 4552d 09h /minsoc/branches/rc-1.0/backend/std/configure
69 backend update:
Both files should now be under minsoc/backend to proper system functionality.
backend subdirectories have been given those files. Configure script updated accordingly.

They are searched there from system scripts and Makefiles.
-sim/bin/minsoc_verilog_files.txt has the files for Icarus Verilog, minsoc_bench_defines.v is now referenced from backend directory.
-sw/support/ now references to inside backend.

-It is the system configuration for Spartan 3E Starter Kit with Ethernet.
rfajardo 4676d 07h /minsoc/branches/rc-1.0/backend/std/configure
65 Files missing in the last commit.
sw: eth, uart and driver Makefiles
rfajardo 4678d 12h /minsoc/branches/rc-1.0/backend/std/configure

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