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[/] [minsoc/] [branches/] [rc-1.0/] [bench/] [verilog/] - Rev 130

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9 Tiny change to testbench gain:
-uart_srx is now reg for future testbench serial input to SoC.
rfajardo 4066d 13h /minsoc/branches/rc-1.0/bench/verilog/
8 Cosmetic changes to minsoc_bench.v:
-reset and clock initialization are included into the main initial block, it had an own block before
rfajardo 4066d 13h /minsoc/branches/rc-1.0/bench/verilog/
7 Some changes:
-wb_cabs removed from minsoc_top.v and minsoc_tc_top.v
-added reset polarity control to minsoc_defines.v through:
-POSITIVE_RESET
-NEGATIVE_RESET
-minsoc_onchip_ram_top.v does not use
minsoc_onchip_ram.v oe signals (output enable) anymore,
which are implemented as tristate buffers. Now
minsoc_onchip_ram_top.v has a generated MUX, which
has an arbitrary number of inputs and 1 output.
Input are the internal output of the onchip_rams,
output the wb_dat_o.
rfajardo 4071d 14h /minsoc/branches/rc-1.0/bench/verilog/
4 minsoc_bench.v had a big memory declaration to load the firmware, which was not necessary.

jp-io-vpi.vpi has to be compiled for different systems so removed from the project. Documentation now explains how to do it.

Documentation now includes:
-vpi module compilation
-gdb patch for adv_jtag_bridge
-ideas for future work on minsoc (To Do v.2)
rfajardo 4081d 19h /minsoc/branches/rc-1.0/bench/verilog/
2 First commit of project. Beta status:
-testbench: working
-firmware: working
-RTL: Working for: Xilinx Spartan-3A DSP Development Kit
rfajardo 4085d 18h /minsoc/branches/rc-1.0/bench/verilog/

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