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[/] [minsoc/] [branches/] [rc-1.0/] [bench/] [verilog/] [minsoc_bench.v] - Rev 133

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133 Roll back minsoc_bench.v to timed simulation. Merge minsoc_bench_core and minsoc_bench_clock again.

Applying Rubén Diez patch to avoid warnings on firmware load for simulation.
rfajardo 4776d 23h /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench.v

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