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[/] [minsoc/] [branches/] [rc-1.0/] [bench/] [verilog/] [minsoc_memory_model.v] - Rev 130

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109 Creating a branche for release candidate 1.0. rfajardo 3319d 21h /minsoc/branches/rc-1.0/bench/verilog/minsoc_memory_model.v
71 Modelsim whines about missing timescales:
-minsoc_bench.v, minsoc_memory_model.v and dbg_comm_vpi.v updated to include timescale.v

modelsim simulation working under Windows. Modelsim PE Student Edition 10.0a

Simulation<->adv_jtag_bridge<->gdb communication not working perfectly. I believe VPI module has to be recompiled, used pre-compiled one for now.
rfajardo 3489d 06h /minsoc/branches/rc-1.0/bench/verilog/minsoc_memory_model.v
60 Selection of memory model or implementation memory is now made on minsoc_bench_defines.v. It is done by a definition instead of including different files for simulation.

minsoc_bench_defines.v definition of reset level was not correct. It based the level decision on defineds POSITIVE_RESET or NEGATIVE_RESET, which couldn't be defined by then, since minsoc_defines.v is not included in minsoc_bench_defines.v. The decision has been moved to minsoc_bench.v and made a localparam instead of a definition.
rfajardo 3500d 18h /minsoc/branches/rc-1.0/bench/verilog/minsoc_memory_model.v
2 First commit of project. Beta status:
-testbench: working
-firmware: working
-RTL: Working for: Xilinx Spartan-3A DSP Development Kit
rfajardo 4088d 05h /minsoc/branches/rc-1.0/bench/verilog/minsoc_memory_model.v

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