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[/] [minsoc/] [branches/] [rc-1.0/] [prj/] [src/] [minsoc_bench.prj] - Rev 133

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133 Roll back minsoc_bench.v to timed simulation. Merge minsoc_bench_core and minsoc_bench_clock again.

Applying Rubén Diez patch to avoid warnings on firmware load for simulation.
rfajardo 3683d 08h /minsoc/branches/rc-1.0/prj/src/minsoc_bench.prj
131 Renaming testbench modules. Adding to ifdefs without which the testbench generation can fail. rfajardo 3687d 04h /minsoc/branches/rc-1.0/prj/src/minsoc_bench.prj
128 Outsourcing clocks and reset generations from minsoc_bench.v to minsoc_bench_clock.v. rfajardo 3687d 18h /minsoc/branches/rc-1.0/prj/src/minsoc_bench.prj
109 Creating a branche for release candidate 1.0. rfajardo 3694d 22h /minsoc/branches/rc-1.0/prj/src/minsoc_bench.prj
88 Project structure, Xilinx Makefiles and simulation working. rfajardo 3745d 01h /minsoc/branches/rc-1.0/prj/src/minsoc_bench.prj

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