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Rev Log message Author Age Path
109 Creating a branche for release candidate 1.0. rfajardo 3744d 02h /minsoc/branches/rc-1.0/prj/xilinx/
97 As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. rfajardo 3788d 13h /minsoc/branches/rc-1.0/prj/xilinx/
91 prj/scripts/: Changing scripts not to include multiple timescale.v files from different listed directories in the project definition file. Instead, now the internal loop which look for the file in different directories is broken when the first file is found. rfajardo 3793d 13h /minsoc/branches/rc-1.0/prj/xilinx/
90 After minsoc_top.prj update, make regenerated src and xst files. rfajardo 3794d 05h /minsoc/branches/rc-1.0/prj/xilinx/
88 Project structure, Xilinx Makefiles and simulation working. rfajardo 3794d 05h /minsoc/branches/rc-1.0/prj/xilinx/
85 Central project definition under prj. Synthesis and simulation take their project files from here. rfajardo 3794d 07h /minsoc/branches/rc-1.0/prj/xilinx/

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