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[/] [minsoc/] [branches/] [rc-1.0/] [rtl/] [verilog/] [altera_pll.v] - Rev 147

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109 Creating a branche for release candidate 1.0. rfajardo 3369d 19h /minsoc/branches/rc-1.0/rtl/verilog/altera_pll.v
63 Adding a functional synthesis Makefile system. Still needs a reviews and enhancements, but at least it is something. rfajardo 3549d 21h /minsoc/branches/rc-1.0/rtl/verilog/altera_pll.v
62 Wrapping different family modules of same manufacturer in a single module.

minsoc_clock_manager.v: uses fpga manufacturer wrappers

xilinx_dcm.v: selects between different Xilinx FPGA families and implements the module

altera_pll.v: selects between different Altera FPGA families and implements the module
rfajardo 3550d 04h /minsoc/branches/rc-1.0/rtl/verilog/altera_pll.v
56 Macros for all Altera family devices and pll instantiation javieralso 3557d 16h /minsoc/branches/rc-1.0/rtl/verilog/altera_pll.v
52 Altera ALTPLL Megafunction Instantiation javieralso 3567d 18h /minsoc/branches/rc-1.0/rtl/verilog/altera_pll.v

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