URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [rc-1.0/] [rtl/] [verilog/] [altera_pll.v] - Rev 56

Rev	Log message	Author	Age	Path
56	Macros for all Altera family devices and pll instantiation	javieralso	4753d 22h	/minsoc/branches/rc-1.0/rtl/verilog/altera_pll.v
52	Altera ALTPLL Megafunction Instantiation	javieralso	4764d 00h	/minsoc/branches/rc-1.0/rtl/verilog/altera_pll.v