| Rev |
Log message |
Author |
Age |
Path |
| 57 |
If a FPGA manufacturer is selected, the FPGA families of other manufacturers are automatically ignored.
Some updated to comments.
CLOCK_DIVISOR back to 5. The number does not matter much, but 1 is a bad standard number, since it should never be selected. Comment says, use NO_CLOCK_DIVISION instead.
Changing standard FPGA back to Xilinx and Spartan3A. I'm only doing this because the synthesis examples page of wiki still assume this FPGA to be standardly selected. |
rfajardo |
4415d 03h |
/minsoc/branches/rc-1.0/rtl/verilog |
| 56 |
Macros for all Altera family devices and pll instantiation |
javieralso |
4422d 01h |
/minsoc/branches/rc-1.0/rtl/verilog |
| 53 |
Indentation, deleting redundant files and adding externals |
ConX. |
4423d 13h |
/minsoc/branches/rc-1.0/rtl/verilog |
| 52 |
Altera ALTPLL Megafunction Instantiation |
javieralso |
4432d 03h |
/minsoc/branches/rc-1.0/rtl/verilog |
| 33 |
Start-up Starter, included in the MinSoC top file, has been updated to three-phase instruction output; instruction assertion, acknowledge assertion, and next instruction with acknowledge deassertion.
Previously it was two-phase with next instruction, instruction assertion and acknowledge assertion together, and acknowledge deassertion.
That is required by the new Wishbone master interface used by OpenRISC release 3. |
rfajardo |
4618d 11h |
/minsoc/branches/rc-1.0/rtl/verilog |
| 31 |
Adaption to or1200_r3. It is still important to change or1200_defines.v:
-`define OR1200_BOOT_ADR 32'hf0000100 to `define OR1200_BOOT_ADR 32'h00000100 |
rfajardo |
4687d 16h |
/minsoc/branches/rc-1.0/rtl/verilog |
| 26 |
On version 34 of the Advanced Debug System the signal debug_tdo_o from the altera_virtual_jtag has changed to debug_tdo_i.
This commit adapts minsoc_top.v accordingly. |
rfajardo |
4797d 22h |
/minsoc/branches/rc-1.0/rtl/verilog |
| 20 |
minsoc_defines.v had a semicolon at the end of the two reset polarity definitions.
minsoc_top had a signal array for two different signals which was for backward compatibility. The compatible debugging module is so old that there is no reason for keeping it.
Documentation has been updated to better explain how to use the definitions files, minsoc_defines.v and or1200_defines.v. An example for Altera devices has been added too. |
rfajardo |
4877d 10h |
/minsoc/branches/rc-1.0/rtl/verilog |
| 17 |
Ethernet testbench speed penalty solved. Now Ethernet of testbench and minsoc can be enabled by only uncommenting `define ETHERNET on minsoc_defines.v.
send_mac, get_mac and uart_send tasks have been included/improved. Also a testbench, which works for both included firmwares is added. (eth and uart)
If ETHERNET is defined for the SoC, both firmwares will complete successfully. If not, the eth firmware will stall when trying to access the Ethernet module. |
rfajardo |
4942d 09h |
/minsoc/branches/rc-1.0/rtl/verilog |
| 16 |
Further initialization improvement of non-used signals, setting interrupt signals to 0 if module is not used. |
rfajardo |
4947d 13h |
/minsoc/branches/rc-1.0/rtl/verilog |
| 14 |
Wishbone error signal of Ethernet core was not tied to ground if Ethernet was disabled. Solved now. |
rfajardo |
4956d 14h |
/minsoc/branches/rc-1.0/rtl/verilog |
| 12 |
1) spi_top.v:
-TX_NEGEDGE bug reported and recommended solution by Blaise Gassend. (Thank you)
2) minsoc howto extended to:
-synthesis of minsoc for Spartan3E Starter Kit with Ethernet
3) spartan3e_starter_kit.ucf changed:
-it had problems regarding pin definitions and IO logic types for mapping and place&route. Working flawless now. |
rfajardo |
4960d 05h |
/minsoc/branches/rc-1.0/rtl/verilog |
| 7 |
Some changes:
-wb_cabs removed from minsoc_top.v and minsoc_tc_top.v
-added reset polarity control to minsoc_defines.v through:
-POSITIVE_RESET
-NEGATIVE_RESET
-minsoc_onchip_ram_top.v does not use
minsoc_onchip_ram.v oe signals (output enable) anymore,
which are implemented as tristate buffers. Now
minsoc_onchip_ram_top.v has a generated MUX, which
has an arbitrary number of inputs and 1 output.
Input are the internal output of the onchip_rams,
output the wb_dat_o. |
rfajardo |
4988d 08h |
/minsoc/branches/rc-1.0/rtl/verilog |
| 6 |
No implementation relevant changes.
Testbench used generic memory from minsoc_onchip_ram.v has been changed to reflect the correct model of the FPGA's onchip rams: address register and write accesses are sensitive to rising clock edge.
Documentation updated to reflect another trial and next steps to speed up the memory access from 2 clocks to 1. The negated clock approach is not standard. The right way to do it would be to use the wishbone signals cti and bte and change the minsoc_onchip_ram_top.v. |
rfajardo |
4992d 14h |
/minsoc/branches/rc-1.0/rtl/verilog |
| 2 |
First commit of project. Beta status:
-testbench: working
-firmware: working
-RTL: Working for: Xilinx Spartan-3A DSP Development Kit |
rfajardo |
5002d 12h |
/minsoc/branches/rc-1.0/rtl/verilog |
