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[/] [minsoc/] [branches/] [rc-1.0/] [utils/] [setup/] [] - Rev 115


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Rev Log message Author Age Path
115 script dir aware. logging to script dir.
rfajardo 3281d 11h /minsoc/branches/rc-1.0/utils/setup/
113 &
-aware of location of script
-does not block on patch error

spartan3e_starter_kit & spartan3e_starter_kit_eth:
-or1200_defines.v updated

-src/blackboxes/or1200_top.v adjusted to or1200_rel1
-Makefile had a typo regarding altera vhdl files
rfajardo 3281d 11h /minsoc/branches/rc-1.0/utils/setup/
112 Updating installation & configuration scripts. rfajardo 3282d 03h /minsoc/branches/rc-1.0/utils/setup/
110 Fixing several minor issues with the system:
-minsoc-install splitted into installation and configuration can be used to configure a fresh checked out system
-configure script used by both and to configure

-rtl/verilog: svn externals fixed
-or1200 rolled back to release-1.0

-Makefile has been used by simulation to differentiate project definition of vhdl and verilog files
-Altera was differentiating it in script
-now there are two scripts, one for vhdl and another for verilog. The differentiation occurs in Makefile as for simulation.
-altera_3c25_board/configure scripts had to be updated, vprj and vhdprj file extensions used to differentiate Verilog and VHDL project files.

-prj/src: or1200_top.prj downdated to definition of or1200_v1
rfajardo 3282d 04h /minsoc/branches/rc-1.0/utils/setup/

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