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[/] [minsoc/] [branches/] [rc-1.0] - Rev 132

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Rev Log message Author Age Path
112 Updating installation & configuration scripts. rfajardo 4573d 18h /minsoc/branches/rc-1.0
111 minsoc-install.sh: DIR_TO_INSTALL is required before using beautify.sh rfajardo 4573d 19h /minsoc/branches/rc-1.0
110 Fixing several minor issues with the system:
-minsoc-install splitted into installation and configuration
-minsoc-configure.sh can be used to configure a fresh checked out system
-configure script used by both minsoc-configure.sh and minsoc-install.sh to configure

-rtl/verilog: svn externals fixed
-or1200 rolled back to release-1.0

-prj/scripts:
-Makefile has been used by simulation to differentiate project definition of vhdl and verilog files
-Altera was differentiating it in script
-now there are two scripts, one for vhdl and another for verilog. The differentiation occurs in Makefile as for simulation.
-altera_3c25_board/configure scripts had to be updated, vprj and vhdprj file extensions used to differentiate Verilog and VHDL project files.

-prj/src: or1200_top.prj downdated to definition of or1200_v1		 rfajardo 4573d 19h /minsoc/branches/rc-1.0
109 Creating a branche for release candidate 1.0. rfajardo 4573d 21h /minsoc/branches/rc-1.0
108 Scripts updates to correct paths when working under Windows. Now, ModelSim, Xilinx and Altera synthesis are working on Windows through batch files.

Icarus Verilog and Altera synthesis are working as well. Job done!		 rfajardo 4574d 00h /minsoc/trunk
107 Adding setup batch script for Altera synthesis on Windows.

prj/scripts/altprj.sh has now to check if it is run from cygwin in order to re-formulate the path to windows system.

Maybe the other scripts have to be updated too. This will be checked soon.		 rfajardo 4574d 03h /minsoc/trunk
106 Installation script was checking the ENV variable before setting it. rfajardo 4574d 06h /minsoc/trunk
105 Updating configure scripts to copy Windows synthesis launch script setup.bat from either minsoc/syn/altera or minsoc/syn/xilinx to minsoc/syn. rfajardo 4574d 08h /minsoc/trunk
104 Enabling modelsim simulation for current project definition.
vhdl and verilog projects have to be separated:
-prj/Makefile defines VHDL_PROJECTS and VERILOG_PROJECTS, they are merged into PROJECTS. Tools which don't care about VHDL or Verilog use PROJECTS list while other tools use VERILOG_ or VHDL_PROJECTS.
-Simulation uses VHDL_PROJECTS and VERILOG_PROJECTS independently.
-prj/scripts/simprj.sh splitted in:
-simvhdl.sh
-simverilog.sh
(they generate the input files in the right format for simulation tools)		 rfajardo 4581d 07h /minsoc/trunk
103 But the file is called gdb-6.8a.tar.bz2, so tar must be run on that name. rfajardo 4583d 22h /minsoc/trunk

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