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Rev Log message Author Age Path
99 backend/altera_3c25_board/minsoc_defines.v: if GENERIC_FPGA selected, undefine ALTERA_FPGA and FPGA_FAMILY to avoid vendor specific code to flow into the simulation. If you don't do it, generate_bench fails. rfajardo 4619d 17h /minsoc/branches/verilator/
98 Removing deprecated minsoc_top.qsf file. rfajardo 4619d 17h /minsoc/branches/verilator/
97 As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. rfajardo 4619d 17h /minsoc/branches/verilator/
96 Some files needed for Altera synthesis javieralso 4620d 04h /minsoc/branches/verilator/
95 Makefile for Altera FPGAs fixed javieralso 4621d 07h /minsoc/branches/verilator/
94 Fix bug in minsoc_top.prj for Altera synthesis javieralso 4623d 16h /minsoc/branches/verilator/
93 Support for Altera synthesis. It needs some tune, but it works fine javieralso 4623d 19h /minsoc/branches/verilator/
92 backend/spartan3e_starter_kit*: or1200_defines.v file was outdated and hindering synthesis. Probably it would be best if we used a patching system here. But for now, I copied the new files and made the necessary changes to fit the system into the target boards. rfajardo 4624d 17h /minsoc/branches/verilator/
91 prj/scripts/: Changing scripts not to include multiple timescale.v files from different listed directories in the project definition file. Instead, now the internal loop which look for the file in different directories is broken when the first file is found. rfajardo 4624d 18h /minsoc/branches/verilator/
90 After minsoc_top.prj update, make regenerated src and xst files. rfajardo 4625d 09h /minsoc/branches/verilator/

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