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Rev Log message Author Age Path
96 Some files needed for Altera synthesis javieralso 4616d 05h /minsoc/branches/verilator/
95 Makefile for Altera FPGAs fixed javieralso 4617d 08h /minsoc/branches/verilator/
94 Fix bug in minsoc_top.prj for Altera synthesis javieralso 4619d 17h /minsoc/branches/verilator/
93 Support for Altera synthesis. It needs some tune, but it works fine javieralso 4619d 19h /minsoc/branches/verilator/
92 backend/spartan3e_starter_kit*: or1200_defines.v file was outdated and hindering synthesis. Probably it would be best if we used a patching system here. But for now, I copied the new files and made the necessary changes to fit the system into the target boards. rfajardo 4620d 17h /minsoc/branches/verilator/
91 prj/scripts/: Changing scripts not to include multiple timescale.v files from different listed directories in the project definition file. Instead, now the internal loop which look for the file in different directories is broken when the first file is found. rfajardo 4620d 18h /minsoc/branches/verilator/
90 After minsoc_top.prj update, make regenerated src and xst files. rfajardo 4621d 10h /minsoc/branches/verilator/
89 minsoc_top.prj was splited into minsoc_top and minsoc_bench. minsoc_top still had directory entries of bench, they are gone now. rfajardo 4621d 10h /minsoc/branches/verilator/
88 Project structure, Xilinx Makefiles and simulation working. rfajardo 4621d 10h /minsoc/branches/verilator/
87 Synchronizing scripts to behave exactly the same. rfajardo 4621d 11h /minsoc/branches/verilator/
86 Updating configure script messages. rfajardo 4621d 11h /minsoc/branches/verilator/
85 Central project definition under prj. Synthesis and simulation take their project files from here. rfajardo 4621d 11h /minsoc/branches/verilator/
84 syn/blackboxes/eth_top.v:
-module is now called ethmac instead of eth_top
-eth_defines.v is now called ethmac_defines.v		 rfajardo 4622d 12h /minsoc/branches/verilator/
83 minsoc-install.sh: bzip2 program was being used, but its existance on target system was not being verified. It is now. rfajardo 4633d 17h /minsoc/branches/verilator/
82 minsoc-install.sh: problems with copying the GNU Toolchain from download to tools. We uncompress the GNU Toolchain now once again to tools during the installation part. rfajardo 4636d 17h /minsoc/branches/verilator/
81 Installation script complete, nice text feedback, output logs and better execution order. rfajardo 4637d 04h /minsoc/branches/verilator/
80 Establishing a better Makefile system for firmwares. rfajardo 4639d 16h /minsoc/branches/verilator/
79 minsoc-install.sh: rpath corrected.
required-cygwin-tools: updated		 rfajardo 4640d 09h /minsoc/branches/verilator/
78 minsoc-install.sh: Advanced JTAG bridge compilation needs to know where the dynamic libraries are on runtime. Patching (sed) the Makefile to compile it with the rpath to the libraries (libusb/libftdi). rfajardo 4640d 09h /minsoc/branches/verilator/
77 New tool requirements for installing Icarus Verilog. rfajardo 4640d 09h /minsoc/branches/verilator/

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