Rev |
Log message |
Author |
Age |
Path |
97 |
As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. |
rfajardo |
4634d 10h |
/minsoc/branches/verilator/ |
96 |
Some files needed for Altera synthesis |
javieralso |
4634d 21h |
/minsoc/branches/verilator/ |
95 |
Makefile for Altera FPGAs fixed |
javieralso |
4636d 00h |
/minsoc/branches/verilator/ |
94 |
Fix bug in minsoc_top.prj for Altera synthesis |
javieralso |
4638d 08h |
/minsoc/branches/verilator/ |
93 |
Support for Altera synthesis. It needs some tune, but it works fine |
javieralso |
4638d 11h |
/minsoc/branches/verilator/ |
92 |
backend/spartan3e_starter_kit*: or1200_defines.v file was outdated and hindering synthesis. Probably it would be best if we used a patching system here. But for now, I copied the new files and made the necessary changes to fit the system into the target boards. |
rfajardo |
4639d 09h |
/minsoc/branches/verilator/ |
91 |
prj/scripts/: Changing scripts not to include multiple timescale.v files from different listed directories in the project definition file. Instead, now the internal loop which look for the file in different directories is broken when the first file is found. |
rfajardo |
4639d 10h |
/minsoc/branches/verilator/ |
90 |
After minsoc_top.prj update, make regenerated src and xst files. |
rfajardo |
4640d 01h |
/minsoc/branches/verilator/ |
89 |
minsoc_top.prj was splited into minsoc_top and minsoc_bench. minsoc_top still had directory entries of bench, they are gone now. |
rfajardo |
4640d 02h |
/minsoc/branches/verilator/ |
88 |
Project structure, Xilinx Makefiles and simulation working. |
rfajardo |
4640d 02h |
/minsoc/branches/verilator/ |
87 |
Synchronizing scripts to behave exactly the same. |
rfajardo |
4640d 03h |
/minsoc/branches/verilator/ |
86 |
Updating configure script messages. |
rfajardo |
4640d 03h |
/minsoc/branches/verilator/ |
85 |
Central project definition under prj. Synthesis and simulation take their project files from here. |
rfajardo |
4640d 03h |
/minsoc/branches/verilator/ |
84 |
syn/blackboxes/eth_top.v:
-module is now called ethmac instead of eth_top
-eth_defines.v is now called ethmac_defines.v |
rfajardo |
4641d 04h |
/minsoc/branches/verilator/ |
83 |
minsoc-install.sh: bzip2 program was being used, but its existance on target system was not being verified. It is now. |
rfajardo |
4652d 09h |
/minsoc/branches/verilator/ |
82 |
minsoc-install.sh: problems with copying the GNU Toolchain from download to tools. We uncompress the GNU Toolchain now once again to tools during the installation part. |
rfajardo |
4655d 08h |
/minsoc/branches/verilator/ |
81 |
Installation script complete, nice text feedback, output logs and better execution order. |
rfajardo |
4655d 19h |
/minsoc/branches/verilator/ |
80 |
Establishing a better Makefile system for firmwares. |
rfajardo |
4658d 08h |
/minsoc/branches/verilator/ |
79 |
minsoc-install.sh: rpath corrected.
required-cygwin-tools: updated |
rfajardo |
4659d 00h |
/minsoc/branches/verilator/ |
78 |
minsoc-install.sh: Advanced JTAG bridge compilation needs to know where the dynamic libraries are on runtime. Patching (sed) the Makefile to compile it with the rpath to the libraries (libusb/libftdi). |
rfajardo |
4659d 01h |
/minsoc/branches/verilator/ |