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[/] [minsoc/] [branches/] [verilator/] [backend/] [altera_3c25_board/] [minsoc_defines.v] - Rev 139

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139 Creating a verilator branche. rfajardo 4699d 13h /minsoc/branches/verilator/backend/altera_3c25_board/minsoc_defines.v
109 Creating a branche for release candidate 1.0. rfajardo 4726d 03h /minsoc/branches/verilator/backend/altera_3c25_board/minsoc_defines.v
99 backend/altera_3c25_board/minsoc_defines.v: if GENERIC_FPGA selected, undefine ALTERA_FPGA and FPGA_FAMILY to avoid vendor specific code to flow into the simulation. If you don't do it, generate_bench fails. rfajardo 4770d 13h /minsoc/branches/verilator/backend/altera_3c25_board/minsoc_defines.v
95 Makefile for Altera FPGAs fixed javieralso 4772d 04h /minsoc/branches/verilator/backend/altera_3c25_board/minsoc_defines.v
93 Support for Altera synthesis. It needs some tune, but it works fine javieralso 4774d 15h /minsoc/branches/verilator/backend/altera_3c25_board/minsoc_defines.v

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