URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [verilator/] [prj/] [sim/] - Rev 153

Rev	Log message	Author	Age	Path
139	Creating a verilator branche.	rfajardo	4547d 21h	/minsoc/branches/verilator/prj/sim/
109	Creating a branche for release candidate 1.0.	rfajardo	4574d 11h	/minsoc/branches/verilator/prj/sim/
97	As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board.	rfajardo	4618d 22h	/minsoc/branches/verilator/prj/sim/
91	prj/scripts/: Changing scripts not to include multiple timescale.v files from different listed directories in the project definition file. Instead, now the internal loop which look for the file in different directories is broken when the first file is found.	rfajardo	4623d 23h	/minsoc/branches/verilator/prj/sim/
90	After minsoc_top.prj update, make regenerated src and xst files.	rfajardo	4624d 14h	/minsoc/branches/verilator/prj/sim/
88	Project structure, Xilinx Makefiles and simulation working.	rfajardo	4624d 14h	/minsoc/branches/verilator/prj/sim/
85	Central project definition under prj. Synthesis and simulation take their project files from here.	rfajardo	4624d 16h	/minsoc/branches/verilator/prj/sim/