OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [verilator/] [prj/] [xilinx/] - Rev 164

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
139 Creating a verilator branche. rfajardo 4766d 12h /minsoc/branches/verilator/prj/xilinx/
109 Creating a branche for release candidate 1.0. rfajardo 4793d 02h /minsoc/branches/verilator/prj/xilinx/
97 As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. rfajardo 4837d 13h /minsoc/branches/verilator/prj/xilinx/
91 prj/scripts/: Changing scripts not to include multiple timescale.v files from different listed directories in the project definition file. Instead, now the internal loop which look for the file in different directories is broken when the first file is found. rfajardo 4842d 14h /minsoc/branches/verilator/prj/xilinx/
90 After minsoc_top.prj update, make regenerated src and xst files. rfajardo 4843d 05h /minsoc/branches/verilator/prj/xilinx/
88 Project structure, Xilinx Makefiles and simulation working. rfajardo 4843d 05h /minsoc/branches/verilator/prj/xilinx/
85 Central project definition under prj. Synthesis and simulation take their project files from here. rfajardo 4843d 07h /minsoc/branches/verilator/prj/xilinx/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.