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[/] [minsoc/] [branches/] [verilator/] [rtl/] [verilog/] [altera_pll.v] - Rev 140

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Rev Log message Author Age Path
139 Creating a verilator branche. rfajardo 3832d 04h /minsoc/branches/verilator/rtl/verilog/altera_pll.v
109 Creating a branche for release candidate 1.0. rfajardo 3858d 18h /minsoc/branches/verilator/rtl/verilog/altera_pll.v
63 Adding a functional synthesis Makefile system. Still needs a reviews and enhancements, but at least it is something. rfajardo 4038d 20h /minsoc/branches/verilator/rtl/verilog/altera_pll.v
62 Wrapping different family modules of same manufacturer in a single module.

minsoc_clock_manager.v: uses fpga manufacturer wrappers

xilinx_dcm.v: selects between different Xilinx FPGA families and implements the module

altera_pll.v: selects between different Altera FPGA families and implements the module
rfajardo 4039d 03h /minsoc/branches/verilator/rtl/verilog/altera_pll.v
56 Macros for all Altera family devices and pll instantiation javieralso 4046d 15h /minsoc/branches/verilator/rtl/verilog/altera_pll.v
52 Altera ALTPLL Megafunction Instantiation javieralso 4056d 17h /minsoc/branches/verilator/rtl/verilog/altera_pll.v

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