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140 Including required modules for verilator simulation. rfajardo 3228d 16h /minsoc/branches/verilator/rtl/verilog/minsoc_top.v
139 Creating a verilator branche. rfajardo 3228d 16h /minsoc/branches/verilator/rtl/verilog/minsoc_top.v
109 Creating a branche for release candidate 1.0. rfajardo 3255d 06h /minsoc/branches/verilator/rtl/verilog/minsoc_top.v
75 Adapting minsoc_top.v and minsoc_verilog_files.txt to new names for top modules and define file of ethmac ip core. rfajardo 3331d 09h /minsoc/branches/verilator/rtl/verilog/minsoc_top.v
60 Selection of memory model or implementation memory is now made on minsoc_bench_defines.v. It is done by a definition instead of including different files for simulation.

minsoc_bench_defines.v definition of reset level was not correct. It based the level decision on defineds POSITIVE_RESET or NEGATIVE_RESET, which couldn't be defined by then, since minsoc_defines.v is not included in minsoc_bench_defines.v. The decision has been moved to minsoc_bench.v and made a localparam instead of a definition.
rfajardo 3436d 04h /minsoc/branches/verilator/rtl/verilog/minsoc_top.v
56 Macros for all Altera family devices and pll instantiation javieralso 3443d 04h /minsoc/branches/verilator/rtl/verilog/minsoc_top.v
52 Altera ALTPLL Megafunction Instantiation javieralso 3453d 05h /minsoc/branches/verilator/rtl/verilog/minsoc_top.v
33 Start-up Starter, included in the MinSoC top file, has been updated to three-phase instruction output; instruction assertion, acknowledge assertion, and next instruction with acknowledge deassertion.

Previously it was two-phase with next instruction, instruction assertion and acknowledge assertion together, and acknowledge deassertion.

That is required by the new Wishbone master interface used by OpenRISC release 3.
rfajardo 3639d 13h /minsoc/branches/verilator/rtl/verilog/minsoc_top.v
31 Adaption to or1200_r3. It is still important to change or1200_defines.v:
-`define OR1200_BOOT_ADR 32'hf0000100 to `define OR1200_BOOT_ADR 32'h00000100
rfajardo 3708d 18h /minsoc/branches/verilator/rtl/verilog/minsoc_top.v
26 On version 34 of the Advanced Debug System the signal debug_tdo_o from the altera_virtual_jtag has changed to debug_tdo_i.

This commit adapts minsoc_top.v accordingly.
rfajardo 3819d 01h /minsoc/branches/verilator/rtl/verilog/minsoc_top.v
20 minsoc_defines.v had a semicolon at the end of the two reset polarity definitions.

minsoc_top had a signal array for two different signals which was for backward compatibility. The compatible debugging module is so old that there is no reason for keeping it.

Documentation has been updated to better explain how to use the definitions files, minsoc_defines.v and or1200_defines.v. An example for Altera devices has been added too.
rfajardo 3898d 12h /minsoc/branches/verilator/rtl/verilog/minsoc_top.v
17 Ethernet testbench speed penalty solved. Now Ethernet of testbench and minsoc can be enabled by only uncommenting `define ETHERNET on minsoc_defines.v.

send_mac, get_mac and uart_send tasks have been included/improved. Also a testbench, which works for both included firmwares is added. (eth and uart)

If ETHERNET is defined for the SoC, both firmwares will complete successfully. If not, the eth firmware will stall when trying to access the Ethernet module.
rfajardo 3963d 12h /minsoc/branches/verilator/rtl/verilog/minsoc_top.v
16 Further initialization improvement of non-used signals, setting interrupt signals to 0 if module is not used. rfajardo 3968d 15h /minsoc/branches/verilator/rtl/verilog/minsoc_top.v
14 Wishbone error signal of Ethernet core was not tied to ground if Ethernet was disabled. Solved now. rfajardo 3977d 16h /minsoc/branches/verilator/rtl/verilog/minsoc_top.v
7 Some changes:
-wb_cabs removed from minsoc_top.v and minsoc_tc_top.v
-added reset polarity control to minsoc_defines.v through:
-POSITIVE_RESET
-NEGATIVE_RESET
-minsoc_onchip_ram_top.v does not use
minsoc_onchip_ram.v oe signals (output enable) anymore,
which are implemented as tristate buffers. Now
minsoc_onchip_ram_top.v has a generated MUX, which
has an arbitrary number of inputs and 1 output.
Input are the internal output of the onchip_rams,
output the wb_dat_o.
rfajardo 4009d 10h /minsoc/branches/verilator/rtl/verilog/minsoc_top.v
2 First commit of project. Beta status:
-testbench: working
-firmware: working
-RTL: Working for: Xilinx Spartan-3A DSP Development Kit
rfajardo 4023d 14h /minsoc/branches/verilator/rtl/verilog/minsoc_top.v

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