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[/] [minsoc/] [branches/] [verilator/] [sim/] [modelsim/] - Rev 142

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Rev Log message Author Age Path
139 Creating a verilator branche. rfajardo 4547d 19h /minsoc/branches/verilator/sim/modelsim/
134 run_sim.bat for ModelSim updated to acquire the firmware_size for command line input when running the testbench. rfajardo 4562d 18h /minsoc/branches/verilator/sim/modelsim/
133 Roll back minsoc_bench.v to timed simulation. Merge minsoc_bench_core and minsoc_bench_clock again.

Applying Rubén Diez patch to avoid warnings on firmware load for simulation.		 rfajardo 4562d 19h /minsoc/branches/verilator/sim/modelsim/
132 ModelSim simulation, running top_module minsoc_bench_clock now, instead of minsoc_bench. rfajardo 4566d 15h /minsoc/branches/verilator/sim/modelsim/
121 Asserting svn:executable properties of modelsim/*.bat scripts.

Including corrected patch for advanced debug system watchpoints under utils/setup. Configure script updated to use this instead of advanced debug system patches. This will remain so until the patch is corrected. The previous line still has the correct command.		 rfajardo 4573d 10h /minsoc/branches/verilator/sim/modelsim/
119 Tricking Subversion to accept bat files that are now executable. rfajardo 4573d 13h /minsoc/branches/verilator/sim/modelsim/
109 Creating a branche for release candidate 1.0. rfajardo 4574d 09h /minsoc/branches/verilator/sim/modelsim/
104 Enabling modelsim simulation for current project definition.
vhdl and verilog projects have to be separated:
-prj/Makefile defines VHDL_PROJECTS and VERILOG_PROJECTS, they are merged into PROJECTS. Tools which don't care about VHDL or Verilog use PROJECTS list while other tools use VERILOG_ or VHDL_PROJECTS.
-Simulation uses VHDL_PROJECTS and VERILOG_PROJECTS independently.
-prj/scripts/simprj.sh splitted in:
-simvhdl.sh
-simverilog.sh
(they generate the input files in the right format for simulation tools)		 rfajardo 4581d 19h /minsoc/branches/verilator/sim/modelsim/
85 Central project definition under prj. Synthesis and simulation take their project files from here. rfajardo 4624d 14h /minsoc/branches/verilator/sim/modelsim/
73 Makefile does not automatic clean anymore. In Windows rm -f leads to errors and abort synthesis.

minsoc/syn/setup.bat added. Asks for Xilinx settings32|64.bat script and completely implements MinSoC. On completion or error, it holds window open until user input ENTER.

minsoc/sim/modelsim/: *.bat holds window open until user input ENTER.
run_sim.bat asks for target firmware, check if it exists before running simulator. Holds window open and output error message if not found. Does not hold for simulator.		 rfajardo 4743d 15h /minsoc/branches/verilator/sim/modelsim/
72 Adding Windows batch files to run a Modelsim simulation.
-prepare_modelsim.bat, compile_design.bat, run_sim.bat		 rfajardo 4743d 16h /minsoc/branches/verilator/sim/modelsim/
70 Including a global timescale under minsoc/rtl/verilog to control simulation. It is under the implementation because the implementation files include it.

Removing timescale definition of minsoc_bench_defines.v files.

Creating a modelsim simulation directory. Everything is working under Linux. For Windows, run_sim.sh has to be changed:
-pli ../../bench/verilog/vpi/jp-io-vpi.so
to:
-pli ../../bench/verilog/vpi/jp-io-vpi.dll

These files have to be compiled/copied from minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/modelsim_platform to minsoc/bench/verilog/vpi.		 rfajardo 4743d 19h /minsoc/branches/verilator/sim/modelsim/

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